Over the last decade, gallium nitride (GaN) has emerged as an excellent material for the fabrication of power devices. Among the semiconductors for which power devices are already available in the market, GaN has the widest energy gap, the largest critical field, and the highest saturation velocity, thus representing an excellent material for the fabrication of high-speed/high-voltage components. The presence of spontaneous and piezoelectric polarization allows us to create a two-dimensional electron gas, with high mobility and large channel density, in the absence of any doping, thanks to the use of AlGaN/GaN heterostructures. This contributes to minimize resistive losses; at the same time, for GaN transistors, switching losses are very low, thanks to the small parasitic capacitances and switching charges. Device scaling and monolithic integration enable a high-frequency operation, with consequent advantages in terms of miniaturization. For high power/high-voltage operation, vertical device architectures are being proposed and investigated, and three-dimensional structures—fin-shaped, trench-structured, nanowire-based—are demonstrating great potential. Contrary to Si, GaN is a relatively young material: trapping and degradation processes must be understood and described in detail, with the aim of optimizing device stability and reliability. This Tutorial describes the physics, technology, and reliability of GaN-based power devices: in the first part of the article, starting from a discussion of the main properties of the material, the characteristics of lateral and vertical GaN transistors are discussed in detail to provide guidance in this complex and interesting field. The second part of the paper focuses on trapping and reliability aspects: the physical origin of traps in GaN and the main degradation mechanisms are discussed in detail. The wide set of referenced papers and the insight into the most relevant aspects gives the reader a comprehensive overview on the present and next-generation GaN electronics.

https://hal.archives-ouvertes.fr/hal-03421528/document

GaN-based power devices: Physics, reliability, and perspectives

In this paper, numerical device simulations are used to point out the possible contributions of carbon doping to the threshold voltage instabilities induced by negative gate bias stress in AlGaN/GaN metal–insulator–semiconductor high-electron mobility transistors. It is suggested that carbon can have a role in both negative and positive threshold voltage shifts, as a result of (1) the changes in the total negative charge stored in the carbon-related acceptor traps in the GaN buffer, and (2) the attraction of carbon-related free holes to the device surface and their capture into interface traps or recombination with gate-injected electrons. For a proper device optimization of carbon-doped MIS-HEMTs, it is therefore important to take these mechanisms into account, in addition to those related to defects in the gate dielectric volume and interface which are conventionally held responsible for threshold voltage instabilities.

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The effects of carbon on the bidirectional threshold voltage instabilities induced by negative gate bias stress in GaN MIS-HEMTs

Electrical performances degradations and physics based mechanisms under negative bias temperature instability stress for p-GaN gate high electron mobility transistors

Parasitic capacitances associated with overhangs of the T-shape-gate enhancement-mode (E-mode) GaN-based power device, were investigated by frequency/voltage-dependent capacitance–voltage and inductive-load switching measurements. The overhang capacitances induce a pinch-off voltage distinguished from that of the E-mode channel capacitance in the gate capacitance and the gate–drain capacitance characteristic curves. Frequency- and voltage-dependent tests confirm the instability caused by the trapping of interface/bulk states in the LPCVD-SiN x passivation dielectric. Circuit-level double pulse measurement also reveals its impact on switching transition for power switching applications.

Instability of parasitic capacitance in T-shape-gate enhancement-mode AlGaN/GaN MIS-HEMTs

In this paper, we propose a novel characterization methodology to study dynamic RON and VTH during a high voltage stress on the drain node of GaN-on-Si E-mode MOSc-HEMTs using a half-bridge configuration circuit and specific gate voltage waveforms. This novel setup enables to study simultaneously RON and VTH during stress and recovery phases from 10µs to several kiloseconds. At 150°C a high carbon concentration in Carbon-doped GaN layer, reduces ON-Resistance degradation. Temperature dependent measurements show that RON degradation is related to CN acceptor traps in the GaN:C layer. High voltage drain stress induces a combination of VTH drift and access region related dynamic RON effect.

Novel High Voltage Bias Temperature Instabilities (HV-BTI) setup to monitor RON/VTH drift on GaN-on-Si E-mode MOSc-HEMTs under drain voltage

In this paper, we investigate the influence of negative gate stress on threshold voltage V TH instabilities in GaN-on-Si devices. This study has been carried out by using ultra-fast Measurement-Stress-Measurement (MSM) procedure on GaN-on-Si E-mode MOSc-HEMTs (Enhancement-mode MOS-channel HEMTs) for different gate lengths L G . NBTI transients at different temperatures and complementary ToF-SIMS analysis reveal the influence of two trap populations involved on V TH instabilities, both of them are related to the C N acceptor traps. The first one is close to the interface between GaN and Al 2 O 3 gate oxide due to N-vacancies induced by the dry etching process, the second one is likely to be related to GaN:C layer. NBTI transients also exhibit a dependence with L G , which is consistent with the E-field distribution of the gate region obtained by TCAD simulations at different gate stress voltages, and confirm the proximity of a C N trap population to the gate oxide.

J.-P. Barnes

Papers

Investigation of nBTI degradation on GaN-on-Si E-mode MOSc-HEMT