Analysis methods are developed that fully determine a switched-capacitor (SC) dc-dc converter's steady-state performance through evaluation of its output impedance. This analysis method has been verified through simulation and experimentation. The simple formulation developed permits optimization of the capacitor sizes to meet a constraint such as a total capacitance or total energy storage limit, and also permits optimization of the switch sizes subject to constraints on total switch conductances or total switch volt-ampere (V-A) products. These optimizations then permit comparison among several switched-capacitor topologies, and comparisons of SC converters with conventional magnetic-based dc-dc converter circuits, in the context of various application settings. Significantly, the performance (based on conduction loss) of a ladder-type converter is found to be superior to that of a conventional magnetic-based converter for medium to high conversion ratios.

Analysis and Optimization of Switched-Capacitor DC–DC Converters

Multilevel power converters that provide more than two levels of voltage to achieve smoother and less distorted AC-to-DC, DC-to-AC, and DC-to-DC power conversion, have attracted many contributors. This paper presents a generalized multilevel inverter (converter) topology with self voltage balancing. The existing multilevel inverters such as diode-clamped and capacitor-clamped multilevel inverters can be derived from the generalized inverter topology. Moreover, the generalized multilevel inverter topology provides a true multilevel structure that can balance each DC voltage level automatically without any assistance from other circuits, thus, in principle, providing a complete and true multilevel topology that embraces the existing multilevel inverters. From this generalized multilevel inverter topology, several new multilevel inverter structures can be derived. Some application examples of the generalized multilevel converter are given.

A generalized multilevel inverter topology with self voltage balancing

Analysis methods are developed that fully determine a switched-capacitor (SC) DC-DC converter's steady-state performance through evaluation of its output impedance. The simple formulation developed permits optimization of the capacitor sizes to meet a constraint such as a total capacitance or total energy storage limit, and also permits optimization of the switch sizes subject to constraints on total switch conductances or total switch volt-ampere (V-A) products. These optimizations then permit comparison among the switched-capacitor topologies, and comparisons of SC converters with conventional magnetic-based DC-DC converter circuits, in the context of various application settings. Significantly, the performance (based on conduction loss) of a ladder-type converter is found to be superior to that of a conventional boost converter for medium to high conversion ratios

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Analysis and Optimization of Switched-Capacitor DC-DC Converters

The theoretical performance limits of two-phase switched-capacitor (SC) DC-DC power converters are discussed in this paper. For a given number of capacitors k, the complete set of attainable DC conversion ratios is found. The maximum step-up or step-down ratio is given by the k/sup th/ Fibonacci number, while the bound on the number of switches required in any SC circuit is 3k-2. Practical implications, illustrated by several SC power converter examples, include savings in the number of components required for a given application, and the ability to construct SC power converters that can maintain the output voltage regulation and high conversion efficiency over a wide range of input voltage variations. Limits found for the output resistance and efficiency can be used for selection and comparison of SC power converters. >

Performance limits of switched-capacitor DC-DC converters

A Design Methodology for Switched-Capacitor DC-DC Converters

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An expression for the equivalent source resistance of the capacitor diode voltage multiplier circuit is derived. The source resistance is found to increase as the cube of the multiplication factor, explaining the poor regulation observed with large multiplication. The distribution of capacitors that minimizes source resistance is presented. Good regulation is shown to be necessary for high efficiency, and to require relatively larger capacitors than needed for ripple filtering.

J.S. Brugler

Papers

Theoretical performance of voltage multiplier circuits