Properties of the current-driven passive mixer are explored to maximize its performance in a zero-IF receiver. Since there is no reverse isolation between the RF and baseband sides of the mixer, the mixer reflects the baseband impedance to the RF and vice versa through simple frequency shifting. It is also shown that in an IQ down-conversion system the lack of reverse isolation causes a mutual interaction between the two quadrature mixers, which results in different high- and low-side conversion gains, and unexpected IIP2 and IIP3 values. With a thorough and accurate mathematical analysis it is shown how to design this mixer and its current buffer, and how to size components to get the best linearity, conversion gain and noise figure while alleviating the IQ cross-talk problem.

Analysis and Optimization of Current-Driven Passive Mixers in Narrowband Direct-Conversion Receivers

A broadband CMOS direct-conversion receiver with on-chip frequency divider has been integrated in a 0.13- μm CMOS process. The key feature of the proposed receiver front-end is a single low-noise transconductance amplifier (LNTA) driving a current-mode passive mixer terminated by a low-input-impedance transimpedance amplifier (TIA). The receiver chain has improved robustness to out-of-band interference and outstanding linearity. We employ a broadband common-gate (CG) LNTA with dual feedback to improve both gain and noise figure (NF) without breaking the fixed relationship between input impedance, transconductance gain, and load impedance. A LNTA load impedance boosting technique suppresses noise-amplification due to TIA, commonly found in passive mixers. The core circuit (RF and baseband signal path) consumes only 13 mW, and the prototype receiver achieves >22.4-dB conversion gain, dB NF, and ≥ -1.5 dBm IIP3 from 1.4 to 5.2 GHz. Maximum conversion gain of 24.3 dB and minimum NF of 6.5 dB are achieved at 1.4 and 2 GHz, respectively. The chip active area is 1.1 mm 2 with the entire RF signal path operated from a 1.2-V supply. The LO portion is biased from a 1.5-V supply.

Low-Power, Low-Cost CMOS Direct-Conversion Receiver Front-End for Multistandard Applications

.......................................................................................................................... I Acknowledgement ......................................................................................................... IV TABLE OF CONTENTS ............................................................................................... V LIST OF FIGURES .................................................................................................... VIII LIST OF TABLES ........................................................................................................ XI 1. Chapter 1: Introduction ............................................................................................ 1 1.1 Motivation......................................................................................................... 1 1.2 Objective and Major contributions..................................................................... 2 1.3 Thesis organization ........................................................................................... 4 2. Chapter 2: Literature review on LNA design ............................................................ 5 2.1 Receiver architectures ....................................................................................... 5 2.1.1 Heterodyne Receiver .................................................................................. 5 2.1.2 Homodyne Receiver (Direct conversion receiver)....................................... 7 2.2 Design parameters ............................................................................................. 9 2.2.1 Sensitivity .................................................................................................. 9 2.2.2 Noise figure ............................................................................................... 9 2.2.3 Harmonic distortion and Intermodulation ................................................. 12 2.2.4 Dynamic Range ........................................................................................ 17 2.2.5 S-Parameters ............................................................................................ 18 2.3 Introduction to LNA ........................................................................................ 20 2.3.1 Performance trade-offs in LNA design ..................................................... 22 2.3.2 Input Architecture .................................................................................... 29 2.3.3 Tuning techniques of LNA's Load ............................................................ 40

/pdf/ultra-low-power-low-noise-amplifier-designs-for-2-4-ghz-ism-27z3ei8ykz.pdf

Ultra low-power low-noise amplifier designs for 2.4 GHz ISM band applications

A fully integrated transmit chain for 802.11a band with on-chip power amplifier and on-chip balun matching network in 45nm standard digital CMOS process demonstrates saturated power of +23dBm. The average efficiency is +5% and peak efficiency is +15%. A standalone class AB CMOS power amplifier with on-chip BALUN matching network was also produced and detailed characterization data is presented. Using digital predistortion, an EVM of −28dB is achieved at 19dBm for 5GHz band and 2.5GHz band for standalone Power Amplifier.

Fully integrated 23dBm transmit chain with on-chip power amplifier and balun for 802.11a application in standard 45nm CMOS process

A baseband transimpedance amplifier for coexisting radio receivers is presented. It exploits active feedback to improve out-of-band large-signal attenuation, minimizing in-band distortion due to close-in blockers. A fully-differential prototype of the proposed solution has been designed and implemented in 45nm CMOS. Experimental results show that it can handle linearly single tones of ±10mA, withstanding blocking currents of ±9mA at 50MHz and beyond before reaching P1dB in a 10MHz bandwidth. The fabricated device occupies 0.25mm2, largely MOM finger capacitors, and draws 17mA from a 2.5V supply.

A large-signal blocker robust transimpedance amplifier for coexisting radio receivers in 45nm CMOS

A multi-standard direct conversion receiver achieves 2.2 dB NF at 6 GHz with a 15 kHz flicker noise corner. 1 dB RF bandwidth is 4.9-6 GHz, power dissipation is 56 mW from 1.3 V and active die area is less than 1.2 mm2, including the input matching network. Inband P1 dB and IIP3 at maximum gain (39 dB) are -30 dBm and -18 dBm, respectively, and three gain steps of 6 dB are provided. DC offset from self mixing is less than 10 mV.

J.S. Duster

Papers

A 2.2dB NF, 4.9–6GHz direct conversion multi-standard RF receiver front-end in 90nm CMOS