J
Jade Alglave
Researcher at University College London
Publications - 43
Citations - 2371
Jade Alglave is an academic researcher from University College London. The author has contributed to research in topics: Concurrency & Sequential consistency. The author has an hindex of 22, co-authored 43 publications receiving 2123 citations. Previous affiliations of Jade Alglave include Queen Mary University of London & French Institute for Research in Computer Science and Automation.
Papers
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Journal ArticleDOI
Understanding POWER multiprocessors
TL;DR: An abstract-machine semantics that abstracts from most of the implementation detail but explains the behaviour of a range of subtle examples of IBM POWER multiprocessors is given, which should bring new clarity to concurrent systems programming for these architectures.
Journal ArticleDOI
Herding Cats: Modelling, Simulation, Testing, and Data Mining for Weak Memory
TL;DR: In this article, the authors propose an axiomatic generic framework for weak memory modeling, which allows the user to specify the model of his choice in a concise way, and the tool becomes a simulator for that model.
Book ChapterDOI
Partial Orders for Efficient Bounded Model Checking ofźConcurrentźSoftware
TL;DR: An efficient encoding into integer difference logic for bounded model checking that enables first-time formal verification of deployed concurrent systems code is obtained.
Proceedings ArticleDOI
The semantics of x86-CC multiprocessor machine code
Susmit Sarkar,Peter Sewell,Francesco Zappa Nardelli,Scott Owens,Tom Ridge,Thomas Braibant,Magnus O. Myreen,Jade Alglave +7 more
TL;DR: In this paper, a rigorous and accurate semantics for x86 multiprocessor programs, from instruction decoding to relaxed memory model, mechanised in HOL, has been developed for programs that are data-race free.
Book ChapterDOI
Fences in weak memory models
TL;DR: A class of relaxed memory models, defined in Coq, parameterised by the chosen permitted local reorderings of reads and writes, and the visibility of inter- and intra-processor communications through memory is presented.