International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

The Foundations of Statistics By Prof. Leonard J. Savage. (Wiley Publications in Statistics.) Pp. xv + 294. (New York; John Wiley and Sons, Inc.; London: Chapman and Hall, Ltd., 1954.) 48s. net.

Probability and Statistical Inference

Introduction to quality engineering : designing quality into products and processes

IEEE transactions on computer-aided design of integrated circuits and systems : a publication of the IEEE Circuits and Systems Society

VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

This paper studies the behavior of stuck and resistive open defects The effects on test results of three test conditions (supply voltage, speed, temperature) as well as test patterns applied are evaluated Diagnosis schemes for stuck and resistive opens are also presented Five Murphy chips are diagnosed as having stuck open defects and one chip is diagnosed as having a resistive open defect Their experimental data match our expectations for stuck opens and resistive opens

Testing for resistive opens and stuck opens

Scan-based testing has proven to be a cost-effective method for achieving good test coverage in digital circuits. The Achilles heel in the application of scan-based testing is the integrity of the scan chains. The amount of die area consumed by scan elements, chain connections, and control circuitry varies with different designs. Typically, each scan cell in a scan chain has an index number. The cells in the chain are sequentially numbered from scan output to scan input, starting with 0. A chain pattern (sometimes called a flush pattern) is a pattern consisting of shift-in and shift-out operations without pulsing capture clocks. The purpose of chain patterns is to test scan chain integrity. A scan pattern (also known as a logic test pattern) is a pattern consisting of a shift-in operation, one or multiple capture clock cycles, and a shift-out operation. The purpose of scan patterns is to test system logic. The scan cells between the scan chain input and a scan cell's scan input terminal are called the upstream cells of that scan cell. The scan cells between the scan chain output and a scan cell's scan output terminal are called the downstream cells of that scan cell.

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Survey of Scan Chain Diagnosis

This paper presents a secure test wrapper (STW) design that is compatible with the IEEE 1500 standard. STW protects not only internal scan chains but also primary inputs and outputs, which may contain critical information (such as encryption keys) during the system operation. To reduce the STW area, flip-flops in the wrapper boundary cells also serve as the LFSR to generate the golden key. Experimental results on an AES core show that STW provides very high security at the price of only 5% area overhead with respect to the original IEEE 1500 test wrapper.

A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores

A technique capable of diagnosing single and multiple stuck-open and stuck-at faults is presented. Eleven sequence-dependent chips (test results depend on the order of test patterns) are diagnosed. Seven of them are diagnosed as having single stuck-open faults. Two of them are diagnosed as having multiple stuck-at and stuck-open faults.

Diagnosis of sequence-dependent chips

LSI logic has designed and manufactured two test chips at CRC. These test chips were used to investigate the characteristics of actual production defects and the effectiveness of various test techniques in detecting their presence. This paper presents a characterization of the defects that shows that very few defective chips act as if they had a single-stuck fault present and that most of the defects cause sequence-dependent behavior. A variety of techniques are used to reduce the size of test sets for digital chips. They typically rely on preserving the single-stuck-fault coverage of the test set. This strategy doesn't guarantee that the defect coverage is retained. This paper presents data obtained from applying a variety of test sets on two chips (Murphy and ELF35) and recording the test escapes. The reductions in test size can thus be compared with the increases in test escapes. The data shows that, even when the fault coverage is preserved, there is a penalty in test quality. Also presented is the data showing the effect of reducing the fault coverage. Techniques studied include various single-stuck-fault models including inserting faults at the inputs of complex gates such as adders, multiplexers, etc. This technique is compatible with the use of structural RTL netlists. Other techniques presented include compaction techniques and don't care bit assignment strategies.

/pdf/elf-murphy-data-on-defects-and-tests-sets-548ebovjqk.pdf

James Chien-Mo Li

Papers

Testing for resistive opens and stuck opens

Survey of Scan Chain Diagnosis

A Secure Test Wrapper Design Against Internal and Boundary Scan Attacks for Embedded Cores

Diagnosis of sequence-dependent chips

ELF-Murphy data on defects and tests sets