Showing papers in "IEEE Design & Test of Computers in 2008"
TL;DR: The Gigascale Systems Research Center Resilient-System Design Team's goal is to provide highly effective, low-cost solutions to ensure both correctness and reliability in future designs and technology nodes, thereby extending the lifetime of silicon fabrication technologies beyond what can be currently foreseen as profitable.
Abstract: The continued scaling of silicon fabrication technology has led to significant reliability concerns, which are quickly becoming a dominant design challenge. Design integrity is threatened by complexity challenges in the form of immense designs defying complete verification, and physical challenges such as silicon aging and soft errors, which impair correct system operation. The Gigascale Systems Research Center Resilient-System Design Team is addressing these key challenges through synergistic research thrusts, ranging from near-term reliability stress reduction techniques to methods for improving the quality of today's silicon, to longer-term technologies that can detect, recover, and repair faulty systems. These efforts are supported and complemented by an active fault-modeling research effort and a strong focus on functional-verification methodologies. The team's goal is to provide highly effective, low-cost solutions to ensure both correctness and reliability in future designs and technology nodes, thereby extending the lifetime of silicon fabrication technologies beyond what can be currently foreseen as profitable.
124 citations
TL;DR: The difficulty of silicon validation will increase at 65 nm and below because existing ad hoc methodologies don't scale with the unprecedented levels of SoC device complexity.
Abstract: Silicon validation - proving a chip works correctly at speed and in system under different operating conditions - is always necessary, even for a "perfect" design. Silicon debug - finding the root cause of a malfunction - is necessary whenever a design is not flawless. First-silicon validation and debug require a labor-intensive engineering effort of several months and have become the least predictable and most time-consuming part of a new 90-nm chip's development cycle. Lack of adequate tools and automatic procedures is a big factor in this bottleneck. The difficulty of silicon validation will increase at 65 nm and below because existing ad hoc methodologies don't scale with the unprecedented levels of SoC device complexity. Even the most sophisticated SoC design methodology cannot fully account for all the parameters that affect silicon behavior, or for all logic corner cases occurring in the life of a chip working at speed and in system. For example, the simultaneous occurrence of two unlikely events might not be anticipated pre- silicon, so it is never simulated or analyzed; however, when it occurs in system, it can cause unexpected behavior. Presilicon verification methods - simulation, emulation, FPGA prototyping, timing analysis, and formal verification - don't address many deep-submicron problems that occur in the actual device.
119 citations
TL;DR: This article describes the most common structured approaches available for silicon debug of embedded systems and describes the act of adding debug support to a chip's design in the realization that not every silicon chip or embedded-software application is right the first time.
Abstract: Some problems in a new chip design or its embedded software show up only when a silicon prototype of the chip is placed in its intended target environment and the embedded software is executed. Traditionally, embedded-system debug is very difficult and time-consuming because of the intrinsic lack of internal system observability in the target environment. Design for debug (DFD) is the act of adding debug support to a chip's design in the realization that not every silicon chip or embedded-software application is right the first time. In the past few years, functional debug has made significant progress. This article describes the most common structured approaches available for silicon debug of embedded systems.
113 citations
TL;DR: The authors present an alternative approach based on a recently invented digital-microfluidic platform that enables an adaptive cooling technique and shows how it can be adapted for use as a fully reconfigurable, adaptive cooling platform.
Abstract: Thermal management has emerged as an increasingly important aspect of IC design. Elevated die temperatures are detrimental to circuit performance and reliability. Furthermore, hot spots due to spatially nonuniform heat flux in ICs can cause physical stress that further reduces reliability. The authors of this article review various chip-cooling techniques that have been proposed in the literature. They then present an alternative approach based on a recently invented digital-microfluidic platform that enables an adaptive cooling technique. This novel digital-fluid-handling platform uses a phenomenon known as electrowetting so that a vast array of discrete droplets of liquid, ranging from microliters to nanoliters and potentially to picoliters, can be independently moved along a substrate. Although this technology was originally developed for a biological and chemical lab on a chip, the authors show how it can be adapted for use as a fully reconfigurable, adaptive cooling platform.
86 citations
TL;DR: A chain pattern (sometimes called a flush pattern) is a pattern consisting of shift-in and shift-out operations without pulsing capture clocks, and the purpose of chain patterns is to test scan chain integrity.
Abstract: Scan-based testing has proven to be a cost-effective method for achieving good test coverage in digital circuits. The Achilles heel in the application of scan-based testing is the integrity of the scan chains. The amount of die area consumed by scan elements, chain connections, and control circuitry varies with different designs. Typically, each scan cell in a scan chain has an index number. The cells in the chain are sequentially numbered from scan output to scan input, starting with 0. A chain pattern (sometimes called a flush pattern) is a pattern consisting of shift-in and shift-out operations without pulsing capture clocks. The purpose of chain patterns is to test scan chain integrity. A scan pattern (also known as a logic test pattern) is a pattern consisting of a shift-in operation, one or multiple capture clock cycles, and a shift-out operation. The purpose of scan patterns is to test system logic. The scan cells between the scan chain input and a scan cell's scan input terminal are called the upstream cells of that scan cell. The scan cells between the scan chain output and a scan cell's scan output terminal are called the downstream cells of that scan cell.
82 citations
TL;DR: The authors describe the challenges facing the industry as parallel-computing platforms become even more widely available and multicore and many-core architectures are designed.
Abstract: The evolutionary path of microprocessor design includes both multicore and many-core architectures. Harnessing the most computing throughput from these architectures requires concurrent or parallel execution of instructions. The authors describe the challenges facing the industry as parallel-computing platforms become even more widely available.
74 citations
TL;DR: This efficient approximation model for the drain-source current in a CNFET is analytic, its execution is fast, and it is suitable for simulating circuits consisting of many C NFET devices in a CAD environment.
Abstract: This efficient approximation model for the drain-source current in a CNFET is analytic, its execution is fast, and it is suitable for simulating circuits consisting of many CNFET devices in a CAD environment. Evaluation results show that the model encounters a very modest normalized RMS error for diameter, Fermi level, and bias variations, while significantly improving simulation performance.
72 citations
TL;DR: Two approaches are described to implementing a distributed NoC in a GALS environment to address the difficulty of distributing a synchronous clock signal on the entire chip area.
Abstract: Networks on chips constitute a new design paradigm for communication infrastructures in large multiprocessor SoCs NoCs can use the GALS technique to address the difficulty of distributing a synchronous clock signal on the entire chip area This article describes two approaches to implementing a distributed NoC in a GALS environment
67 citations
TL;DR: In this roundtable, the presenters expounded on the future of multicore chips with respect to education, programming languages, operating systems, and design automation.
Abstract: The 2007 Design Automation Conference (DAC) had a special session entitled "1000 Core Chips," which was organized by Radu Marculescu (Carnegie Mellon University) and Li-Shiuan Peh (Princeton University). This session examined some of the ramifications of multicore chip design from four perspectives: technology, architecture, programming, and design automation. In this roundtable, held immediately following the conference session, the presenters expounded on the future of multicore chips with respect to education, programming languages, operating systems, and design automation.
60 citations
TL;DR: A hybrid-SBST methodology for efficient testing of commercial processor cores that effectively uses the advantages of various SBST methodologies is introduced and applies directed RTPG as a supplement to improve overall fault coverage results.
Abstract: In this article, we introduce a hybrid-SBST methodology for efficient testing of commercial processor cores that effectively uses the advantages of various SBST methodologies. Self-test programs based on deterministic structural SBST methodologies combined with verification-based self-test code development and directed RTPG constitute a very effective H-SBST test strategy. The proposed methodology applies directed RTPG as a supplement to improve overall fault coverage results after component-based self-test code development has been performed.
58 citations
TL;DR: A brief history of test technology research is sketches, tracking the evolution of compression technology that has led to the success of scan compression, and presents the important concepts at a high level on a coarse timeline.
Abstract: The beginnings of the modern-day IC test trace back to the introduction of such fundamental concepts as scan, stuck-at faults, and the D-algorithm. Since then, several subsequent technologies have made significant improvements to the state of the art. Today, IC test has evolved into a multifaceted industry that supports innovation. Scan compression technology has proven to be a powerful antidote to this problem, as it has catalyzed reductions in test data volume and test application time of up to 100 times. This article sketches a brief history of test technology research, tracking the evolution of compression technology that has led to the success of scan compression. It is not our intent to identify specific inventors on a finegrained timeline. Instead, we present the important concepts at a high level, on a coarse timeline. Starting in 1998 and continuing to the present, numerous scan-compression-related inventions have had a major impact on the test landscape. However, this article also is not a survey of the various scan compression methods. Rather, we focus on the evolution of the types of constructs used to create breakthrough solutions.
TL;DR: This article discusses FPGA security problems and current research on reconfigurable devices and security, and presents security primitives and a component architecture for building highly secure systems on FPGAs.
Abstract: FPGAs combine the programmability of processors with the performance of custom hardware. As they become more common in critical embedded systems, new techniques are necessary to manage security in FPGA designs. This article discusses FPGA security problems and current research on reconfigurable devices and security, and presents security primitives and a component architecture for building highly secure systems on FPGAs.
TL;DR: New communication-based models for technologies at the end of, and beyond, the CMOS roadmap are explored.
Abstract: With statistical behavior replacing deterministic behavior in integrated systems, traditional thinking about computation may no longer apply. This article explores new communication-based models for technologies at the end of, and beyond, the CMOS roadmap.
TL;DR: A methodology for analyzing the suitability of error tolerance for a particular application and implementation is presented and is applicable to a broad class of systems.
Abstract: Noise, defects, and process variations are likely to cause very unpredictable circuit performance in future billion-transistor dies, hence decreasing raw yield. Error tolerance is one of several techniques that can increase effective yield. This article presents a methodology for analyzing the suitability of error tolerance for a particular application and implementation. The methodology, illustrated here by a digital telephone-answering device, is applicable to a broad class of systems.
TL;DR: This paper proposes a new approach to reduce test data volume and test cycle count in scan-based testing by assuming a 1-to-1 scan configuration, in which the number of internal scan chains equals thenumber of external scan I/O ports or test channels from ATE.
Abstract: IC testing based on a full-scan design methodology and ATPG is the most widely used test strategy today. However, rapidly growing test costs are severely challenging the applicability of scan-based testing. Both test data size and number of test cycles increase drastically as circuit size grows and feature size shrinks. For a full-scan circuit, test data volume and test cycle count are both proportional to the number of test patterns N and the longest scan chain length L. To reduce test data volume and test cycle count, we can reduce N, L, or both. Earlier proposals focused on reducing the number of test patterns N through pattern compaction. All these proposals assume a 1-to-1 scan configuration, in which the number of internal scan chains equals the number of external scan I/O ports or test channels (two ports per channel) from ATE. Some have shown that ATPG for a circuit with multiple clocks using the multicapture clocking scheme, as opposed to one-hot clocking, generates a reduced number of test patterns.
TL;DR: A design method for handling increasingly dynamic real-time embedded-system applications that reduces the energy consumption of a streaming application running on a single processor platform via dynamic voltage and frequency scaling.
Abstract: A design method for handling increasingly dynamic real-time embedded-system applications can help developers cope with stringent system and market requirements. This method groups an application's operation modes into application scenarios and describes how to incorporate them in the overall design process. An automated scenario-based design trajectory reduces the energy consumption of a streaming application running on a single processor platform via dynamic voltage and frequency scaling.
TL;DR: The underlying speed paths are identified and a detailed analysis on the effects of multiple input switching, cross-coupling noise, and localized voltage drop on microprocessor is performed.
Abstract: In this article, we identify the underlying speed paths and perform a detailed analysis on the effects of multiple input switching, cross-coupling noise, and localized voltage drop on microprocessor. We employ cycle-wise clock shrinks on a tester combined with a CAD methodology to unintrusively identify and analyze these speed paths. Understanding the causes of speed failures can help designers make better power and performance tradeoffs.
TL;DR: The Gigascale Systems Research Center is addressing the complexity, reliability, and productivity challenges of electronic products and their underlying ICs and how it is addressing them.
Abstract: As technology scaling becomes more difficult, continuing advances in electronic products and their underlying ICs increasingly rely on innovative design solutions. This article outlines some of the complexity, reliability, and productivity challenges and how the Gigascale Systems Research Center is addressing them.
TL;DR: This article proposes a flexible scan test methodology called universal multicasting scan (UMC scan), which provides a better than state-of-the-art test compression ratio using multicasting and accepts any existing test patterns and doesn't need ATPG support.
Abstract: Industry has used scan-based designs widely to promote test quality. However, for larger designs, the growing test data volume has significantly increased test cost because of excessively long test times and elevated tester memory and external test channel requirements. To address these problems, researchers have proposed numerous test compression architectures. In this article, we propose a flexible scan test methodology called universal multicasting scan (UMC scan). It has three major features: First, it provides a better than state-of-the-art test compression ratio using multicasting. Second, it accepts any existing test patterns and doesn't need ATPG support. Third, unlike most previous multicasting schemes that use mapping logic to partition the scan chains into hard configurations, UMC scan's compatible scan chain groups are defined by control bits, as in the segmented addressable scan (SAS) architecture. We have developed several techniques to reduce the extra control bits so that the overall test compression ratio can approach that of the ideal multicasting scheme.
TL;DR: This article explores leveraging equalization for global and semi-global long interconnects to overcome the problem of increasing number of cores and off-chip bandwidth demand.
Abstract: As the number of cores increases and onand off-chip bandwidth demand rises, it is becoming increasingly more difficult to rely on conventional interconnects and remain within the chip power budget. This article explores leveraging equalization for global and semi-global long interconnects to overcome this problem.
TL;DR: The goals and ongoing activities of five debug standardization bodies are described: the Nexus 5001, MIPI (Mobile Industry Processor Interface) Test and Debug, IEEE PI149.7, IEEE P1687, and OCP-IP (Open Core Protocol International Partnership) Debug working groups.
Abstract: The semiconductor industry is disaggregated, with a complex web of suppliers and consumers. Standards help to facilitate and simplify the debug process. This article provides an overview of current standardization activity. One area in need of such standardization is that of on-chip debug processes and instruments. The debug area particularly exhibits limited commonality between different IP providers in terms of interfaces and methods for complex SoCs. The problem becomes even greater with more SoC integrators using diverse IP from different vendors, requiring an increasing range of debug, analysis, and optimization capabilities. This article describes the goals and ongoing activities of five debug standardization bodies: the Nexus 5001, MIPI (Mobile Industry Processor Interface) Test and Debug, IEEE PI149.7, IEEE P1687, and OCP-IP (Open Core Protocol International Partnership) Debug working groups.
TL;DR: How, despite an uphill battle, constant innovations keep physical failure analysis going is reported on.
Abstract: Physical failure analysis remains indispensable for final defect confirmation, but is increasingly difficult due to semiconductor technology advances with smaller feature sizes, many metal layers, and flip-chip packaging. This article reports on how, despite an uphill battle, constant innovations keep physical failure analysis going.
TL;DR: The authors of this article characterize these workloads of the future and argue for a new set of benchmarks to guide the exploration and optimization of future systems.
Abstract: Along with changing technologies and design techniques, target applications span a wide range: from large-scale computing to personal services and perceptual interfaces. The authors of this article characterize these workloads of the future and argue for a new set of benchmarks to guide the exploration and optimization of future systems.
TL;DR: This article presents a software framework for communication infrastructure synthesis of distributed systems, which is critical for overall system performance in communication-based design.
Abstract: This article presents a software framework for communication infrastructure synthesis of distributed systems, which is critical for overall system performance in communication-based design. Particular emphasis is given to on-chip interconnect synthesis of multicore designs.
TL;DR: This test-scheduling approach for NoC designs minimizes test time through high-speed test delivery over the network, with test data interleaved via time-division multiplexing (TDM), and through slower test execution at the target cores.
Abstract: This test-scheduling approach for NoC designs minimizes test time through high-speed test delivery over the network, with test data interleaved via time-division multiplexing (TDM), and through slower test execution at the target cores. Results with a test-scheduling algorithm and a simulated test case from ITC 2002 SoC benchmarks show significant test time and I/O savings compared to a single-clock approach.
TL;DR: The principles of the design of embedded electronic systems from the perspective of the entire system, not restricting this perspective to the electrical domain, can help bring system-level design to a new level of efficiency.
Abstract: This article describes the principles of the design of embedded electronic systems from the perspective of the entire system. By not restricting this perspective to the electrical domain, a more disciplined methodology can help bring system-level design to a new level of efficiency.
TL;DR: This article proposes a new methodology for enhancing SoC signal integrity without degrading performance in the presence of power-ground voltage transients through the dynamic adaptation of the clock duty cycle to propagation delay variation along disturbed logic paths.
Abstract: This article proposes a new methodology for enhancing SoC signal integrity without degrading performance in the presence of power-ground voltage transients. The underlying principle is the dynamic adaptation of the clock duty cycle to propagation delay variation along disturbed logic paths. This methodology makes digital circuits more robust to power line fluctuations while maintaining the at-speed clock rate.
TL;DR: This work states that wordor subword-oriented runtime reconfigurable architectures offer highly parallel, scalable solutions combining hardware performance with software flexibility, but they introduce trade-offs in processing-element design.
Abstract: Data-intensive processing in embedded systems is receiving much attention in multimedia computing and high-speed telecommunications. The memory bandwidth problem of traditional von Neumann architectures, however, is impairing processor efficiency. On the other hand, ASIC designs suffer from skyrocketing manufacturing costs and long development cycles. This results in an increasing need for postfabrication programmability at both software and hardware levels. FPGAs provide maximum flexibility with their fine-grained architecture but bring severe overhead in timing, area, and power consumption. Wordor subword-oriented runtime reconfigurable architectures offer highly parallel, scalable solutions combining hardware performance with software flexibility.1 Their coarser granularity reduces area, delay, power consumption, and reconfiguration time, but they introduce trade-offs in processing-element design.
TL;DR: This article shows how the X-compact compression technique in a hierarchical environment can be used to reuse yesterday's chips as modules in today's chips.
Abstract: Capitalizing on the larger capacity of today's ICs, designers are using yesterday's chips as modules in today's chips. DFT methodologies, which usually work on a large, flat design, must begin to take this reuse into account. This article shows how to use the X-compact compression technique in a hierarchical environment.
TL;DR: Circuit-level and full-wave simulations confirm that the proposed design methodology improves signal integrity and power integrity in the UWB transceiver SiP design for a compact implementation in a small mobile platform.
Abstract: Ultrawideband (UWB) wireless communication systems are emerging as a promising solution for high-data-rate and short-distance wireless data transmission. In this article, we introduce a low-noise UWB transceiver SiP design for a compact implementation in a small mobile platform. The SiP's transmitter chip has a fully digital circuit implementation with a passive band-pass filter to meet a US Federal Communications Commission (FCC) regulation, and the receiver chip has a noncoherent architecture. To reduce noise generation and coupling in the densely integrated design, we considered signal integrity issues in the high-frequency channel and power integrity issues on the power distribution network (PDN) in the SiP substrate. Circuit-level and full-wave simulations confirm that the proposed design methodology improves signal integrity and power integrity. The UWB transceiver SiP consists of a fully digital transmitter system and a noncoherent receiver system.