We examine the current performance and future demands of interconnects to and on silicon chips. We compare electrical and optical interconnects and project the requirements for optoelectronic and optical devices if optics is to solve the major problems of interconnects for future high-performance silicon chips. Optics has potential benefits in interconnect density, energy, and timing. The necessity of low interconnect energy imposes low limits especially on the energy of the optical output devices, with a ~ 10 fJ/bit device energy target emerging. Some optical modulators and radical laser approaches may meet this requirement. Low (e.g., a few femtofarads or less) photodetector capacitance is important. Very compact wavelength splitters are essential for connecting the information to fibers. Dense waveguides are necessary on-chip or on boards for guided wave optical approaches, especially if very high clock rates or dense wavelength-division multiplexing (WDM) is to be avoided. Free-space optics potentially can handle the necessary bandwidths even without fast clocks or WDM. With such technology, however, optics may enable the continued scaling of interconnect capacity required by future chips.

Device Requirements for Optical Interconnects to Silicon Chips

An apparatus may include a semiconductor chip and a fluidics assembly. The semiconductor chip has an array of wells and an array of sensors and each sensor of the array of sensors is in fluid communication with a well of the array of wells. The fluidics assembly is located on top of the semiconductor chip and is configured to deliver fluids to the semiconductor chip. The fluidics assembly includes a flow expansion chamber configured to introduce the fluids, an outlet portion configured to pipe out the fluids, and a flow chamber portion. The flow chamber portion is configured to allow the fluids to flow from the flow expansion chamber to the outlet portion and to allow the fluids to interact along the way with material in the array of wells. The flow expansion chamber has a curved wall at the top or bottom so that the height of the flow expansion chamber at the center is less than at the walls that restrict the fluids to the left and right.

Methods and apparatus for measuring analytes using large scale fet arrays

Methods and apparatus relating to FET arrays including large FET arrays for monitoring chemical and/or biological reactions such as nucleic acid sequencing-by-synthesis reactions. Some methods provided herein relate to improving signal (and also signal to noise ratio) from released hydrogen ions during nucleic acid sequencing reactions.

Methods and apparatus for measuring analytes

A catheter and catheter system can use energy tailored for remodeling and/or removal of target material along a body lumen, often of atherosclerotic material of a blood vessel of a patient. An elongate flexible catheter body with a radially expandable structure may have a plurality of electrodes or other electrosurgical energy delivery surfaces to radially engage atherosclerotic material when the structure expands. An atherosclerotic material detector system may measure and/or characterize the atherosclerotic material and its location, optionally using impedance monitoring.

Tuned rf energy and electrical tissue characterization for selective treatment of target tissues

A catheter and catheter system for eccentric remodeling and/or removal of atherosclerotic material of a blood vessel of a patient include an elongate flexible catheter body with a radially expandable structure. A plurality of electrodes or other electrosurgical energy delivery surfaces can radially engage atherosclerotic material when the structure expands. An atherosclerotic material detector near the distal end of the catheter body may measure circumferential atherosclerotic material distribution, and a power source selectively energizes the electrodes to eccentrically remodel the measured atherosclerotic material.

Selectable Eccentric Remodeling and/or Ablation of Atherosclerotic Material

We present a scalable low-power I/O transceiver in 65 nm CMOS, capable of 5-15 Gbps operation over single-board and backplane FR4 channels with power efficiencies between 2.8-6.5 mW/Gbps. Nonlinear power-performance tradeoff is achieved by the use of scalable transceiver circuit blocks and joint optimization of the supply voltage, bias currents and driver power with data rate. Low-power operation is enabled by passive equalization through inductive link termination, active continuous-time RX equalization, global TX/RX clock distribution with on-die transmission lines, and low-noise offset-calibrated receivers.

A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS

A source-synchronous I/O link with adaptive receiver-side equalization has been implemented in 0.13-/spl mu/m bulk CMOS technology. The transceiver is optimized for small area (360 /spl mu/m /spl times/ 360 /spl mu/m) and low power (280 mW). The analog equalizer is implemented as an 8-way interleaved, 4-tap discrete-time linear filter. The equalization improved the data rate of a 102 cm backplane interconnect by 110%. On-die adaptive logic determines optimal receiver settings through comparator offset cancellation, data alignment of the transmitter and receiver, clock de-skew and setting filter coefficients for equalization. The noise-margin degradation due to statistical variation in converged coefficient values was less than 3%.

An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew

Improvements in signaling methods, circuits and process technology have allowed input/output (I/O) data rates to scale beyond 10 Gb/s over several legacy channels. In this regime, it is critical to accurately model and comprehend channel/circuit nonidealities in order to co-optimize the link architecture, circuits, and interconnect. Empirical and worst-case analysis methods used at lower rates are inadequate to account for several deterministic and random noise sources present in I/O links today. In this paper, we review models and methods for statistical signaling analysis of high-speed links, and also propose a new way to integrate behavioral modeling approaches with analytical methods. A computationally efficient segment-based analysis method is shown to accurately capture the effect of transmit jitter and its interaction with the channel. In addition, a new jitter interpretation approach is proposed to enable the analysis of arbitrary I/O clocking topologies. We also present some examples to illustrate the practical utility of these analysis methods in the realm of high-speed I/O design.

Modeling and Analysis of High-Speed I/O Links

A differential amplifier includes a source coupled differential pair of transistors. A feedback loop detects the presence of an input referred offset in the differential amplifier and modifies a body bias voltage on at least one of the transistors in the differential pair. A comparator detects a differential output voltage when the differential input voltage is set to zero. In some embodiments, a charge pump in the feedback loop injects charge on the body of the transistor to modify the bias voltage. In other embodiments, a digital-to-analog converter receives a digital control word and produces a bias voltage on the body of the transistor.

Differential amplifier offset adjustment

A full-duplex transceiver capable of 8-Gb/s data rates is implemented in 0.18-/spl mu/m CMOS. This equalized transceiver has been optimized for small area (329 /spl mu/m /spl times/ 395 /spl mu/m) and low power (158 mW) for point-to-point parallel links. Source-synchronous clocking and per-pin skew compensation eliminate coding bandwidth overhead and reduce latency, jitter, and complexity. This link is self-configuring through the use of automatic comparator offset trim and adaptive deskew. Comprehensive diagnostic capabilities have been integrated into the transceiver to provide link, interconnect, and circuit characterization without the use of external test equipment. With a resolution of 4 mV and 9 ps, these capabilities enable on-die eye diagram generation, equivalent time waveform capture, noise characterization, and jitter distribution measurements.

James E. Jaussi

Papers

A Scalable 5–15 Gbps, 14–75 mW Low-Power I/O Transceiver in 65 nm CMOS

An 8Gb/s source-synchronous I/O link with adaptive receiver equalization, offset cancellation and clock deskew

Modeling and Analysis of High-Speed I/O Links

Differential amplifier offset adjustment

An 8-Gb/s simultaneous bidirectional link with on-die waveform capture