Flash memory is a type of electrically-erasable programmable read-only memory (EEPROM). Because flash memories are nonvolatile and relatively dense, they are now used to store files and other persistent objects in handheld computers, mobile phones, digital cameras, portable music players, and many other computer systems in which magnetic disks are inappropriate. Flash, like earlier EEPROM devices, suffers from two limitations. First, bits can only be cleared by erasing a large block of memory. Second, each block can only sustain a limited number of erasures, after which it can no longer reliably store data. Due to these limitations, sophisticated data structures and algorithms are required to effectively use flash memories. These algorithms and data structures support efficient not-in-place updates of data, reduce the number of erasures, and level the wear of the blocks in the device. This survey presents these algorithms and data structures, many of which have only been described in patents until now.

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Algorithms and data structures for flash memories

Network architecture, computer system and/or server, circuit, device, apparatus, method, and computer program and control mechanism for managing power consumption and workload in computer system and data and information servers. Further provides power and energy consumption and workload management and control systems and architectures for high-density and modular multi-server computer systems that maintain performance while conserving energy and method for power management and workload management. Dynamic server power management and optional dynamic workload management for multi-server environments is provided by aspects of the invention. Modular network devices and integrated server system, including modular servers, management units, switches and switching fabrics, modular power supplies and modular fans and a special backplane architecture are provided as well as dynamically reconfigurable multi-purpose modules and servers. Backplane architecture, structure, and method that has no active components and separate power supply lines and protection to provide high reliability in server environment.

System, method, and architecture for dynamic server power management and dynamic workload management for multi-server environment

A flash-memory system provides solid-state mass storage as a replacement to a hard disk. A unified re-map table in a RAM is used to arbitrarily re-map all logical addresses from a host system to physical addresses of flash-memory devices. Each entry in the unified re-map table contains a physical block address (PBA) of the flash memory allocated to the logical address, and a cache valid bit and a cache index. When the cache valid bit is set, the data is read or written to a line in the cache pointed to by the cache index. A separate cache tag RAM is not needed. When the cache valid bit is cleared, the data is read from the flash memory block pointed to by the PBA. Two write count values are stored with the PBA in the table entry. A total-write count indicates a total number of writes to the flash block since manufacture. An incremental-write count indicates the number of writes since the last wear-leveling operation that moved the block. Wear-leveling is performed on a block being written when both total and incremental counts exceed system-wide total and incremental thresholds. The incremental-write count is cleared after a block is wear-leveled, but the total-write count is never cleared. The incremental-write count prevents moving a block again immediately after wear-leveling. The thresholds are adjusted as the system ages to provide even wear.

Unified re-map and cache-index table with dual write-counters for wear-leveling of non-volatile flash RAM mass storage

System, architecture, and method for logical server and other network devices in a dynamically configurable multi-server network environment

Network architecture, computer system and/or server, circuit, device, apparatus, method, and computer program and control mechanism for managing power consumption and workload in computer system and data and information servers Further provides power and energy consumption and workload management and control systems and architectures for high-density and modular multi-server computer systems that maintain performance while conserving energy and method for power management and workload management Dynamic server power management and optional dynamic workload management for multi-server environments is provided by aspects of the invention Modular network devices and integrated server system, including modular servers, management units, switches and switching fabrics, modular power supplies and modular fans and a special backplane architecture are provided as well as dynamically reconfigurable multi-purpose modules and servers Backplane architecture, structure, and method that has no active components and separate power supply lines and protection to provide high reliability in server environment

Apparatus, architecture, and method for integrated modular server system providing dynamically power-managed and work-load managed network devices

A system for equal utilization of blocks of flash memory whereby a processor using algorithmic software functions to sort the usage-value of each block of flash memory so that the system will select the least-used memory block for the next cycle of memory usage. The described system provides direct and immediate access of flash memory to the microprocessor without any intermediate modules or vias which would delay that access. Further, a minimal amount of overhead header information is only required for each flash memory block thus allowing greater areas of memory usage for instructional code data.

Flash memory wear leveling system providing immediate direct access to microprocessor

A system and method for using standard JTAG protocol for testing protocol compliant and non-protocol compliant digital devices without altering the JTAG protocol or the non-compliant device. A specialized Test Access Port Controller controls and monitors the states applied to the non-compliant device in order to eliminate the PAUSE state in the non-compliant device and to limit the Run-Test/Idle state to one clock period.

JTAG interface system for communicating with compliant and non-compliant JTAG devices

A power network control system has a plurality of digital modules interconnected. A master logic unit in the network communicates with a specialized protocol to slave logic units in each module to provide a reliable power control system for selectively (or generally) instructing modules to turn on or to turn off the local power source.

Power control network using reliable communications protocol

A digital system which normally initializes and tests non-JTAG logic units is adapted to test JTAG protocol compatible logic units. A JTAG translator unit provides an instruction control register and a Data Register. The Control Register has control bits for selecting Test-Mode-Select and Test Clock signals for the JTAG compatible units and Shift/Hold signals for the non-JTAG compatible logic units. The Data Register supplies diagnostic test bits to registers in both the JTAG and non-JTAG logic units. Additionally, the Control Register can initiate automatic incrementation of addresses to a control state RAM for rapid loading of microcode.

System for adapting maintenance operations to JTAG and non-JTAG modules

In a system of multiple digital modules which is operated synchronously via common clock means, there is provided circuitry for halting each module at the same simultaneously clock-moment after sensing of a selected condition in any one of the digital modules.

James Henry Jeppesen

Papers

Flash memory wear leveling system providing immediate direct access to microprocessor

JTAG interface system for communicating with compliant and non-compliant JTAG devices

Power control network using reliable communications protocol

System for adapting maintenance operations to JTAG and non-JTAG modules

System for halting synchronous digital modules