VLSI Test Principles and Architectures: Design for Testability (Systems on Silicon)

This review highlights recent advances towards non-invasive and continuous glucose monitoring devices, with a particular focus placed on monitoring glucose concentrations in alternative physiological fluids to blood.

Glucose Sensing for Diabetes Monitoring: Recent Developments.

In deep sub-micron ICs, growing amounts of on-die memory and scaling effects make embedded memories increasingly vulnerable to reliability and yield problems. As scaling progresses, soft and hard errors in the memory system will increase and single error events are more likely to cause large-scale multi- bit errors. However, conventional memory protection techniques can neither detect nor correct large-scale multi-bit errors without incurring large performance, area, and power overheads. We propose two-dimensional (2D) error coding in embedded memories, a scalable multi-bit error protection technique to improve memory reliability and yield. The key innovation is the use of vertical error coding across words that is used only for error correction in combination with conventional per-word horizontal error coding. We evaluate this scheme in the cache hierarchies of two representative chip multiprocessor designs and show that 2D error coding can correct clustered errors up to 32times32 bits with significantly smaller performance, area, and power overheads than conventional techniques.

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Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding

This book is a comprehensive guide to new DFT methods that will show the readers how to design a testable and quality product, drive down test cost, improve product quality and yield, and speed up time-to-market and time-to-volume.

· Most up-to-date coverage of design for testability. 
· Coverage of industry practices commonly found in commercial DFT tools but not discussed in other books. 
· Numerous, practical examples in each chapter illustrating basic VLSI test principles and DFT architectures.
· Lecture slides and exercise solutions for all chapters are now available.
· Instructors are also eligible for downloading PPT slide files and MSWORD solutions files from the manual website.

Table of Contents

Chapter 1 - Introduction
Chapter 2 - Design for Testability
Chapter 3 - Logic and Fault Simulation 
Chapter 4 - Test Generation 
Chapter 5 - Logic Built-In Self-Test
Chapter 6 - Test Compression
Chapter 7 - Logic Diagnosis
Chapter 8 - Memory Testing and Built-In Self-Test
Chapter 9 - Memory Diagnosis and Built-In Self-Repair
Chapter 10 - Boundary Scan and Core-Based Testing
Chapter 11 - Analog and Mixed-Signal Testing
Chapter 12 - Test Technology Trends in the Nanometer Age

VLSI Test Principles and Architectures: Design for Testability

This book provides a comprehensive description of the architetural techniques to tackle the soft error problem. It covers the new methodologies for quantitative analysis of soft errors as well as novel, cost-effective architectural techniques to mitigate them. To provide readers with a better grasp of the broader problem deffinition and solution space, this book also delves into the physics of soft errors and reviews current circuit and software mitigation techniques. 

TABLE OF CONTENTS
Chapter 1: Introduction 
Chapter 2: Device- and Circuit-Level Modeling, Measurement, and Mitigation 
Chapter 3: Architectural Vulnerability Analysis 
Chapter 4: Advanced Architectural Vulnerability Analysis 
Chapter 5: Error Coding Techniques 
Chapter 6: Fault Detection via Redundant Execution 
Chapter 7: Hardware Error Recovery 
Chapter 8: Software Detection and Recovery

* Provides the methodologies necessary to quantify the effect of radiation-induced soft errors as well as state-of-the-art techniques to protect against them

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Architecture Design for Soft Errors

Foreword. Preface. PART I: CMOS FUNDAMENTALS. 1 Electrical Circuit Analysis. 1.1 Introduction. 1.2 Voltage and Current Laws. 1.3 Capacitors. 1.4 Diodes. 1.5 Summary. Bibliography. Exercises. 2 Semiconductor Physics. 2.1 Semiconductor Fundamentals. 2.2 Intrinsic and Extrinsic Semiconductors. 2.3 Carrier Transport in Semiconductors. 2.4 The pn Junction. 2.5 Biasing the pn Junction: I-V Characteristics. 2.6 Parasitics in the Diode. 2.7 Summary. Bibliography. Exercises. 3 MOSFET Transistors. 3.1 Principles of Operation: Long-Channel Transistors. 3.2 Threshold Voltage in MOS Transistors. 3.3 Parasitic Capacitors in MOS Transistors. 3.4 Device Scaling: Short-Channel MOS Transistors. 3.5 Summary. References. Exercises. 4 CMOS Basic Gates. 4.1 Introduction. 4.2 The CMOS Inverter. 4.3 NAND Gates. 4.4 NOR Gates. 4.5 CMOS Transmission Gates. 4.6 Summary. Bibliography. Exercises. 5 CMOS Basic Circuits. 5.1 Combinational logic. 5.2 Sequential Logic. 5.3 Input-Output (I/O) Circuitry. 5.4 Summary. References. Exercises. PART II FAILURE MODES, DEFECTS, AND TESTING OF CMOS Ics. 6 Failure Mechanisms in CMOS IC Materials. 6.1 Introduction. 6.2 Materials Science of IC Metals. 6.3 Metal Failure Modes. 6.4 Oxide Failure Modes. 6.5 Conclusion. Acknowledgments. Bibliography. Exercises. 7 Bridging Defects. 7.1 Introduction. 7.2 Bridges in ICs: Critical Resistance and Modeling. 7.3 Gate Oxide Shorts (GOS). 7.4 Bridges in Combinational Circuits. 7.5 Bridges in Sequential Circuits. 7.6 Bridging Faults and Technology Scaling. 7.7 Conclusion. References. Exercises. 8 Open Defects. 8.1 Introduction. 8.2 Modeling Floating Nodes in ICs. 8.3 Open Defect Classes. 8.4 Summary. References. Exercises. 9 Parametric Failures. 9.1 Introduction. 9.2 Intrinsic Parametric Failures. 9.3 Intrinsic Parametric Failure Impact on IC Behavior. 9.4 Extrinsic Parametric Failure. 9.5 Conclusion. References. Exercises. 10 Defect-Based Testing. 10.1 Introduction. 10.2 Digital IC Testing: The Basics. 10.3 Design for Test. 10.4 Defect-Based Testing (DBT). 10.5 Testing Nanometer ICs. 10.6 Conclusions. Bibliography. References. Exercises. Appendix A: Solutions to Self-Exercises. A.1 Chapter 1. A.2 Chapter 3. A.3 Chapter 4. A.4 Chapter 5. A.5 Chapter 6. A.6 Chapter 7. A.8 Chapter 8. A.8 Chapter 10. Index. About the Authors.

CMOS Electronics: How It Works, How It Fails

Logic testing has s o m e well known l imi ta t ions f o r circuits with failures causing intermediate voltage levels or, even , correct logic outputs with parametric deuiat ions f r o m the fault free specificattons. For these failures current testing might be considered as a complementary technique t o logic testing. I n this work, these physical defects widely encountered i n ioday’s CMOS processes, are modelled taking into account t h e topology o f the defective circuit and the parameters o f the technology used. These models are used to simulate a t electrical level (SPICE) the behaviour of a simple three inver ter chain wi th a f au l t y inverter. T h e merits o f current testing in f ront of voltage testing are studied for the classes of defects modelled.

Current vs. logic testing of gate oxide short, floating gate and bridging failures in cmos

Defect-based test studies have thoroughly characterized CMOS IC hard bridge and open defects while less is known about a third class called parametric failures. These are more difficult to detect, and their presence is growing in CMOS IC nanoelectronics. The objective of this work is to present data that encompass the electronic properties of parametric failures that affect our ability to test present and future CMOS ICs. While parametric failures are widely reported, we seek to classify these failures with supporting data. Solutions to this complex test problem require that we structure and formalize their behaviors. Data indicate that multiparameter test strategies have the best match to some of the failures while good test strategies do not exist for others.

Parametric failures in CMOS ICs - a defect-based analysis

Many integrated circuit processing defects may cause changes in the value of the quiescent power supply current. Not all of these changes are detectable using classical functional testing techniques. Testing techniques based on the quiescent power supply current inspection have been reported to be efficient in the detection of a wide set of well known physical defects (including bridges and stuck-on). Two quiescent current sensor circuits are proposed and discussed. These circuits are oriented to different testing applications such as the external functional ATE environment, and the built-in self-testing (BIST) design for both on-line and off-line strategies. >

Quiescent current sensor circuits in digital VLSI CMOS testing

Background 
The electronic nose (e-nose) detects volatile organic compounds (VOCs) in exhaled air. We hypothesized that the exhaled VOCs print is different in stable vs. exacerbated patients with chronic obstructive pulmonary disease (COPD), particularly if the latter is associated with airway bacterial infection, and that the e-nose can distinguish them.


Methods 
Smell-prints of the bacteria most commonly involved in exacerbations of COPD (ECOPD) were identified in vitro. Subsequently, we tested our hypothesis in 93 patients with ECOPD, 19 of them with pneumonia, 50 with stable COPD and 30 healthy controls in a cross-sectional case-controlled study. Secondly, ECOPD patients were re-studied after 2 months if clinically stable. Exhaled air was collected within a Tedlar bag and processed by a Cynarose 320 e-nose. Breath-prints were analyzed by Linear Discriminant Analysis (LDA) with “One Out” technique and Sensor logic Relations (SLR). Sputum samples were collected for culture.


Results 
ECOPD with evidence of infection were significantly distinguishable from non-infected ECOPD (p = 0.018), with better accuracy when ECOPD was associated to pneumonia. The same patients with ECOPD were significantly distinguishable from stable COPD during follow-up (p = 0.018), unless the patient was colonized. Additionally, breath-prints from COPD patients were significantly distinguished from healthy controls. Various bacteria species were identified in culture but the e-nose was unable to identify accurately the bacteria smell-print in infected patients.


Conclusion 
E-nose can identify ECOPD, especially if associated with airway bacterial infection or pneumonia.

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Jaume Segura

Papers

CMOS Electronics: How It Works, How It Fails

Current vs. logic testing of gate oxide short, floating gate and bridging failures in cmos

Parametric failures in CMOS ICs - a defect-based analysis

Quiescent current sensor circuits in digital VLSI CMOS testing

Using the Electronic Nose to Identify Airway Infection during COPD Exacerbations