There is, I think, something ethereal about i —the square root of minus one. I remember first hearing about it at school. It seemed an odd beast at that time—an intruder hovering on the edge of reality.

Usually familiarity dulls this sense of the bizarre, but in the case of i it was the reverse: over the years the sense of its surreal nature intensified. It seemed that it was impossible to write mathematics that described the real world in …

I and i

International Technology Roadmap for Semiconductors 2003の要求清浄度について － シリコンウエハ表面と雰囲気環境に要求される清浄度, 分析方法の現状について －

FXT is a software tool which implements inductive fault analysis for CMOS circuits. It extracts a comprehensive list of circuit-level faults for any given CMOS circuit and ranks them according to their relative likelihood of occurrence. Five commercial CMOS circuits are analyzed using FXT. Of the extracted faults, approximately 50% can be modeled by single-line stuck-at 0/1 fault model. Faults extracted from two circuits are simulated with the switch-level fault simulator FMOSSIM. The test set provided by the circuits' manufacturer, which detects 100% of the single-line stuck-at 0/1 faults, detected between 73% and 89% of the simulated faults.<<ETX>>

Extraction and Simulation of Realistic CMOS Faults using

Cadence Design Systems Inc.

IEEE Standard on Piezoelectricity

We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) and a technology-specific part. The first model is based on Shockley equations and is valid for conventional but not deep submicron CMOS. The second model is obtained by fitting SPICE data. The third resistive bridging fault model uses Berkeley predictive technology model and BSIM4; it is valid for CMOS technologies with feature sizes of 90nm and below, accurately describing non-trivial electrical behavior in that technologies. Experimental results for ISCAS circuits show that the test patterns obtained for the Shockley model are still valid for the fitted model, but lead to coverage loss under the predictive model.

/pdf/resistive-bridge-fault-model-evolution-from-conventional-to-234kcdk9jj.pdf

Resistive Bridge fault model evolution from conventional to ultra deep submicron

We study the voltage and current behavior of Gate Oxide Short faults due to pinholes in the gate oxide. Our objective is to give a detailed analysis of the behavior of the GOS defect taking into account random parameters such as the GOS resistance, the GOS location and the GOS size. To facilitate an accurate analysis, we use a bi-dimensional array, and, since a complete analysis is desired, we derive characteristics of the GOS as a function of its resistance, location and size. Finally, we validate the model has been validated through measurements of GOS intentionally injected into a designed and manufactured circuit.

Boolean and current detection of MOS transistor with gate oxide short

In this paper a new model is proposed for gate oxide short defects based on a non-split MOS transistor. Because the MOS is not split, this model allows us to simulate minimum transistors in realistic digital circuits. The construction of the model is presented in detail using a comprehensive and didactic approach. It is demonstrated that the electrical behavior of the proposed model matches in a satisfactory way the defective transistor behavior.

/pdf/modeling-gate-oxide-short-defects-in-cmos-minimum-q2ddjnod8d.pdf

Modeling gate oxide short defects in CMOS minimum transistors

This paper presents a new model for gate-to-channel GOS defects. The transistors used in digital cell library are usually designed with a minimum-size. This new model permits to handle minimal-length transistors allowing the simulation of GOS defects in realistic digital circuits. Based on the electrical analysis of the defect behavior, a comprehensive method for the model construction is detailed. It is shown that the behavior of the proposed model matches in a satisfactory way the behavior of a defective transistor including the random parameters of the defect.

Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short

We investigate the occurrence of Multiple Bit Upsets in commercial SRAMs of 4 Mbits and 32 Mbits when irradiated with neutrons The devices were irradiated at TSL facility with QMN beams of energies from 50 MeV to 180 MeV Experimental data demonstrate that the dynamic-stress increases SRAMs sensitivity as well as MBUs occurrence for both the memory types We also show that both SEU and MBU cross section may depend on memory architecture and memory utilization

Jean-Marc Galliere

Papers

Resistive Bridge fault model evolution from conventional to ultra deep submicron

Boolean and current detection of MOS transistor with gate oxide short

Modeling gate oxide short defects in CMOS minimum transistors

Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short

Neutron-Induced Multiple Bit Upsets on Two Commercial SRAMs Under Dynamic-Stress