The divacancies in SiC are a family of paramagnetic defects that show promise for quantum communication technologies due to their long-lived electron spin coherence and their optical addressability at near-telecom wavelengths. Nonetheless, a high-fidelity spin-photon interface, which is a crucial prerequisite for such technologies, has not yet been demonstrated. Here, we demonstrate that such an interface exists in isolated divacancies in epitaxial films of 3C-SiC and 4H-SiC. Our data show that divacancies in 4H-SiC have minimal undesirable spin mixing, and that the optical linewidths in our current sample are already similar to those of recent remote entanglement demonstrations in other systems. Moreover, we find that 3C-SiC divacancies have a millisecond Hahn-echo spin coherence time, which is among the longest measured in a naturally isotopic solid. The presence of defects with these properties in a commercial semiconductor that can be heteroepitaxially grown as a thin film on Si shows promise for future quantum networks based on SiC defects. DOI:https://doi.org/10.1103/PhysRevX.7.021046 Published by the American Physical Society under the terms of the Creative Commons Attribution 4.0 International license. Further distribution of this work must maintain attribution to the author(s) and the published article’s title, journal citation, and DOI. Published by the American Physical Society

https://link.aps.org/pdf/10.1103/PhysRevX.7.021046

Isolated Spin Qubits in SiC with a High-Fidelity Infrared Spin-to-Photon Interface

SiC power devices have the ability to greatly outperform their Silicon counterparts. SiC material quality and cost issues have largely been overcome, allowing SiC to start competing directly with more traditional Si devices. 150 mm substrates and epitaxy are now commercially available. Commercially released 4H-SiC MOSFETs with a specific on-resistance (R ON,SP ) of 5 mΩcm2 for a 1200 V rating are now available, and research has further optimized the device design and fabrication processes to greatly expand the voltage ratings from 900 V up to 15 kV for a much wider range of high-power, high-frequency energy-conversion applications. Performance for voltage ratings from 900 V up to 15 kV have been achieved with a R ON,SP as low as 2.3 mΩcm2 for a breakdown voltage (BV) of 1230 V and 900 V-rating, 2.7 mΩcm2 for a BV of 1620 V and 1200 V-rating, 10.6 mΩcm2 for a BV of 4160 V and 3300 V-rating, 123 mΩcm2 for a BV of 12 kV and 10 kV-rating, and 208 mΩcm2 for a BV of 15.5 kV and 15 kV-rating. All of these devices exhibit very high frequency switching performance over silicon IGBTs. For even higher voltages, bipolar devices in SiC have been demonstrated from 15 kV up to 27 kV. SiC GTOs have been shown up to 22 kV with 200 A capability. SiC n-IGBTs are reported up to 27 kV, with 20 A capability. This is the highest voltage semiconductor device reported to date.

Silicon carbide power device development for industrial markets

In the last ten years, large improvements in the epitaxial silicon carbide processes have been made. The introduction of chloride precursors, the epitaxial growth on large area substrate with low defect density, the improvement of the surface morphology, the understanding of the chemical vapour deposition (CVD) reactions, and epitaxial mechanisms by advanced simulations are just the main results obtained in the homo-epitaxy process of 4H-SiC. After this large stride in the process of SiC epitaxial growth, it is time to collect this knowledge in a review that can be a reference point for the future work in this interesting field. The structure of the review is the following. After an introduction on the evolution and history of the epitaxial growth of 4H-SiC, the main physics parameter of this epitaxial growth process is explained in detail using the traditional Burton-Cabrera-Franck theory and the experimental observations of the surface instability due to the off-axis growths. Then the introduction of chlorinated precursors in the epitaxial process is reviewed and the effect of this new process on Schottky diodes characteristics is shown. The improvement of the epitaxy process is strictly related to the improvement of the simulation of the growth that helps the researchers to understand the effect of different parameters on such complex system. Then, a large part of the review is devoted to the simulations of the CVD systems, the reaction in the gas phase of the different precursors and the surface reaction models. Also, some important results obtained by Monte Carlo simulation on the study of different growth parameters that influence the formation of defects and their evolution are reported. Finally, the influence of different process parameters and in particular of the growth rate on the formation or the reduction of the principal defects that are observed in the epitaxial layer is reviewed. We have divided these defects in four categories: 3D defects (epi-stacking faults and inclusions), 2D defects (stacking faults), 1D defects (dislocations), and 0D defects (point defects). Also the influences of the growth parameters on the surface morphology (step-bunching) and the correlation with defects have been reviewed. In the conclusions the main results on the chloride epitaxy has been summarized and an outlook of this process in the next years has been presented with the actual understanding of the mechanism of the silicon carbide epitaxial growth.

Mechanisms of growth and defect properties of epitaxial SiC

https://iopscience.iop.org/article/10.1088/1361-6641/aad831/pdf

Review of SiC crystal growth technology

Recent advances in 4H-SiC epitaxy for high-voltage power devices

SiC wafer surface roughness is known to affect the electrical properties of certain power devices. As a result, inspection of the surface roughness can be a very important step for SiC device manufacturing processes. In this paper, we propose a newly fast surface roughness measurement method using Differential Interference Contrast (DIC) microscopy image. Results from this method were compared against white-light interference measurement system and a good correlation was confirmed. The comparison result confirmed that this method was a valid method to measure the surface roughness. This method enables users to inspect the surface roughness in 5 minutes (100mm wafer) and 10 minutes (150mm wafers), respectively.

Jeff Seaman

Papers

Ultra-Fast SiC Wafer Surface Roughness Mapping