Showing papers by "Jenö Dr. Tihanyi published in 1981"

Switch with series-connected MOSFETs

Abstract: Switch with at least two series-connected MOS-FETs has a drain terminal of a preceding MOS-FET connected to a source terminal of a succeeding MOS-FET the MOS-FETs having respective control terminals connectible to a control voltage. The control terminal of the preceding MOS-FET is directly connected to a terminal of the control voltage source. The control terminal of the succeeding MOS-FET is connected to the control terminal of the respective preceding MOS-FET via a diode poled in forward direction with respect to the control voltage source. A resistor is connected between the control terminal and the source terminal of the succeeding MOS-FET.

FET Controlled thyristor

Abstract: Controlled semiconductor switch with a semiconductor body containing a thyristor structure having a first zone of first conductivity type embedded in coplanar relationship in a second zone of second conductivity type; also containing a third zone of the first conductivity type and a fourth zone of the second conductivity type; and further containing an MIS-FET integrated into the semiconductor body and having a source zone of the first conductivity type embedded in coplanar relationship in a zone of the second conductivity type; an insulating layer disposed on the surface of the semiconductor body, a control electrode lying on the insulating layer and covering a first channel zone operatively associated with the FET; and a cathode electrode on the semiconductor body, including the features that the zone of the second conductivity type of the MIS-FET is embedded in the third zone in coplanar relationship therewith and forms the first channel zone at the surface of the semiconductor body; the second zone of the thyristor structure is embedded in the third zone in coplanar relationship therewith and forms a second channel zone at the surface of the semiconductor body; the third zone extends to the surface of the semiconductor body between the two channel zones; the control electrode also covers the second channel zone and the part of the third zone extending to the surface of the semiconductor body; and the cathode electrode is in contact with the source zone of the MIS-FET.

Planar semiconductor with increased breakdown voltage

Abstract: 1. A semiconductor arrangement comprising a substrate (1) of the first conductivity type, a plurality of cells, each having a first zone (3) of the second conductivity type which is embedded in planar fashion in the substrate (1), and each having a second zone (4) of the first conductivity type which is embedded in planar fashion in the first zone (3), wherein, in the first zone (3) at the substrate surface, there is arranged a channel zone (5) which connects the substrate (1) and the second zone (4), and an insulating layer (6) arranged on the substrate surface and on which there is arranged a control electrode (7, 12) which covers at least the channel zone (5), characterized in that, between the first zone (3) of those cells which are adjacent to the edge of the semiconductor arrangement and the edge of the semiconductor arrangement, there is arranged at least one auxiliary electrode (8, 12, 13, 5) which is insulated from the substrate surface ; that the auxiliary electrode (8, 12, 13, 15) has a plurality of sections ; and that the section which is arranged closer to the edge of the semiconductor arrangement is spaced at a greater distance from the surface of the substrate than is the section which is arranged closer to the first zone (3).

Semiconductor controlled switch

Abstract: The invention relates to a controllable semiconductor switch. The on-resistance of which is designed for high voltage MIS-FET is relatively high. Disclosed is a controllable semiconductor switch, in which a thyristor cooperating with a MIS-FET. The cathode electrode (7) contacts the FET (2, 3, 4), while the thyristor (9, 10, 4, 6) has a channel region (13), but no Katodenkontakt. The current is controlled by applying a gate voltage, which opens both the channel region (13) of the thyristor and the channel region (14) of the FET. The current-voltage characteristic similar to a thyristor, the on is low. The semiconductor switch is simply blocked by switching off the gate voltage. The invention is applicable, for example, in motor control applications.

Power MOS transistors for 1000 V blocking voltage

Abstract: High-voltage MOS transistors with blocking voltages of up to 1000 V and turn-on resistances of less than 2 Ω were developed and tested. The transistor structure itself is that of a vertical SIPMOS+(1) power transistor. Retaining this technology, a special design of the cell field and a new type of chip edge construction became necessary in order to achieve the quoted values. The required constructional dimensions were obtained with the aid of a two-dimensional modelling program. (+SIPMOS = Siemens Power MOS)

Vertical mis-field effect transistor with low forward resistance

Abstract: MIS-FET, including a semiconductor substrate of a given first conductivity type having first and second surfaces, at least one channel zone of a second conductivity type opposite the first conductivity type embedded on the first surface of the substrate, a source zone of the first conductivity type embedded in the channel zone, a drain zone adjoining the first surface of the substrate, a drain electrode connected to the second surface of the substrate, and insulating layer disposed on the first surface of the substrate, at least one gate electrode disposed on the insulating layer, at least one injector zone of the second conductivity type embedded in the first surface of the substrate, and a contact being connected to the at least one injector zone and connectible to a voltage supply.

Planare Halbleiteranordnung mit erhöhter Durchbruchsspannung

Abstract: Bei Halbleiterbauelementen mit Planarstruktur, zum Beispiel beim MIS-FET, ist die Durchbruchsspannung im allgemeinen durch die Krummung der Raumladungszone in der Nahe der Oberflache mitbestimmt, die sich am in Sperrichtung vorgespannten pn-Ubergang aufbaut. Die Form der Raumladungszone last sich durch mindestens eine zwischen pn-Ubergang und Substratrand angeordnete Hilfselektrode (8) im Sinne einer Vergroserung des Krummungsradius beeinflussen, die mit zunehmender Entfernung vom pn-Ubergang einen wachsenden Abstand von der Oberflache des Substrats (1) einnimmt. Sie liegt an einer Hilfsspannung, zum Beispiel auf Source-Potential. Die Erfindung ist zum Beispiel bei Hochspannungs-MIS-FET anwendbar.

Schalter mit in Serie geschalteten MOS-FET

Abstract: Die Erfindung bezieht sich auf einen Schalter mit in Serie geschalteten MOS-FET Ein MOS-FET-Schalter fur hohere Spannungen als die Durchbruchsspannung eines einzelnen FET last sich mit einer Serienschaltung mehrerer FET (1, 2, n) aufbauen Dabei ist der Steueranschlus (G) des vorhergehenden FET (1) mit dem des darauffolgenden FET (2) uber ein bezuglich der Steuerspannung in Durchlas gepolten Diode (5) verbunden Die Steueranschlusse des zweiten und der weiteren FET (2, n-1, n) liegen uber je einen Widerstand (6) an ihren Source-Anschlussen (S) Beim Einschalten des vorhergehenden FET sinkt seine Drain-Spannung und die Diode (5) offnet Damit wird der nachfolgende FET eingeschaltet Die Erfindung ist zum Beispiel bei Schaltnetzteilen anwendbar