Showing papers by "Jenö Dr. Tihanyi published in 1998"

A new generation of high voltage MOSFETs breaks the limit line of silicon

Abstract: For the first time a new device concept for high voltage power devices has been realized in silicon. Our 600 V-COOLMOS/sup TM/ reaches an area specific on-resistance of typically 3.5 /spl Omega//spl middot/mm/sup 2/. Our technology thus offers a shrink factor of 5 versus the actual state of the art in power MOSFETs. The device concept is based on charge compensation in the drift region of the transistor. We increase the doping of the vertical drift region roughly by one order of magnitude and counterbalance this additional charge by the implementation of fine structured columns of the opposite doping type. The blocking voltage of the transistor remains thus unaltered. The charge compensating columns do not contribute to the current conduction during the turn-on state. Nevertheless the drastically increased doping of the drift region allows the above mentioned reduction of the on-resistance.

Semiconductor component, such as field-effect power semiconductor device

Abstract: A power field-effect semiconductor component (HLB) includes a number of parallel connected, discrete components (EB) each arranged in cells (Z1...Z6), in which the cells are arranged tightly packed in a cell-field (ZF) in a relatively small space, and consisting of a semiconductor body (1), having at least one inner zone of a first conductivity type, at least one drain zone (4) bordering on the inner zone (2) and with at least one base zone (5) of a second conductivity type arranged in each of the cells (Z1...Z6). At least one source zone (6) of a first conductivity type is arranged in each of the cells (Z1...Z6) and are embedded in the base zones (5). At least one source electrode (7) contacts the base zones (5) and the source zones (6) embedded in the base zones. At least one gate electrode (10) is insulated against the complete semiconductor body (1). Shadowing or masking zones (9) are provided at least in one of the source zones (5) of the cells (Z1...Z4) and reduce the effective W/L (width to length) ratio there, where the W/L ratio describes the ratio of the channel width (W) to the channel length (L).

Source-down fet

Abstract: The invention relates to a source-down FET and a grooved gate (8), wherein a first conductive type drain zone (5) is arranged on the surface of a first conductive type semiconductor layer (3) of a first conductive type semiconductor substrate (1). The grooved gate (8) substantially cross-cuts the semiconductor layer (3). A first conductive type source zone (11) is provided on the end of the groove (8) on the other surface of the semiconductor layer (3) and a second conductive type semiconductor zone (6,7) is located in the area close to the groove (8) on the other surface of the semiconductor layer (3), whereby the surface thereof forms another surface of the semiconductor layer (3), together with the surface of the source zone (11).