Field-effect transistors based on two-dimensional (2D) materials have the potential to be used in very large-scale integration (VLSI) technology, but whether they can be used at the front end of line or at the back end of line through monolithic or heterogeneous integration remains to be determined. To achieve this, multiple challenges must be overcome, including reducing the contact resistance, developing stable and controllable doping schemes, advancing mobility engineering and improving high-κ dielectric integration. The large-area growth of uniform 2D layers is also required to ensure low defect density, low device-to-device variation and clean interfaces. Here we review the development of 2D field-effect transistors for use in future VLSI technologies. We consider the key performance indicators for aggressively scaled 2D transistors and discuss how these should be extracted and reported. We also highlight potential applications of 2D transistors in conventional micro/nanoelectronics, neuromorphic computing, advanced sensing, data storage and future interconnect technologies. This Review examines the development of field-effect transistors based on two-dimensional materials and considers the challenges that need to be addressed for the devices to be incorporated into very large-scale integration (VLSI) technology.

Transistors based on two-dimensional materials for future integrated circuits

The growing importance of applications based on machine learning is driving the need to develop dedicated, energy-efficient electronic hardware. Compared with von Neumann architectures, which have separate processing and storage units, brain-inspired in-memory computing uses the same basic device structure for logic operations and data storage1-3, thus promising to reduce the energy cost of data-centred computing substantially4. Although there is ample research focused on exploring new device architectures, the engineering of material platforms suitable for such device designs remains a challenge. Two-dimensional materials5,6 such as semiconducting molybdenum disulphide, MoS2, could be promising candidates for such platforms thanks to their exceptional electrical and mechanical properties7-9. Here we report our exploration of large-area MoS2 as an active channel material for developing logic-in-memory devices and circuits based on floating-gate field-effect transistors (FGFETs). The conductance of our FGFETs can be precisely and continuously tuned, allowing us to use them as building blocks for reconfigurable logic circuits in which logic operations can be directly performed using the memory elements. After demonstrating a programmable NOR gate, we show that this design can be simply extended to implement more complex programmable logic and a functionally complete set of operations. Our findings highlight the potential of atomically thin semiconductors for the development of next-generation low-power electronics.

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Logic-in-memory based on an atomically thin semiconductor.

Recent advances in organic-based materials for resistive memory applications

Two-dimensional (2D) materials could potentially be used to develop advanced monolithic integrated circuits. However, despite impressive demonstrations of single devices and simple circuits—in some cases with performance superior to those of silicon-based circuits—reports on the fabrication of integrated circuits using 2D materials are limited and the creation of large-scale circuits remains in its infancy. Here we examine the development of integrated circuits based on 2D layered materials. We assess the most advanced circuits fabricated so far and explore the key challenges that need to be addressed to deliver highly scaled circuits. We also propose a roadmap for the future development of integrated circuits based on 2D layered materials. This Perspective examines the development of integrated circuits based on layered two-dimensional materials, exploring where they are likely to first find commercial use and considers the challenges than need to be addressed to create highly scaled circuits.

The development of integrated circuits based on two-dimensional materials

Due to the rapid development of artificial intelligence (AI) and internet of things (IoTs), neuromorphic computing and hardware security are becoming more and more important. The volatile memristors, which feature spontaneous decay of device conductance, own the distinct combination of high similarity to the biological neurons and synapses and unique physical mechanisms. They are excellent candidates for mimicking the synaptic functions and ideal randomness source of the entropy for hardware‐based security. Herein, the recent advances of volatile memristors in devices, mechanisms, and application aspects are summarized. First, a brief introduction is presented to describe the switching type, materials, and temporal response of volatile memristors. Second, the volatile switching mechanisms are discussed and grouped into ion effects, thermal effects, and electrical effects. Third, attention is focused on the applications of volatile memristors for access devices, neuromorphic computing (artificial neurons and synapses), and hardware security (true random number generators and physical unclonable functions). Finally, major challenges and future outlook of volatile memristors for neuromorphic computing and hardware security are discussed.

Recent Advances of Volatile Memristors: Devices, Mechanisms, and Applications

3D monolithic integration of logic and memory has been the most sought after solution to surpass the Von Neumann bottleneck, for which a low-temperature processed material system becomes inevitable. Two-dimensional materials, with their excellent electrical properties and low thermal budget are potential candidates. Here, we demonstrate a low-temperature hybrid co-integration of one-transistor-one-resistor memory cell, comprising a surface functionalized 2D WSe2 p-FET, with a solution-processed WSe2 Resistive Random Access Memory. The employed plasma oxidation technique results in a low Schottky barrier height of 25 meV with a mobility of 230 cm2 V−1 s−1, leading to a 100x performance enhanced WSe2 p-FET, while the defective WSe2 Resistive Random Access Memory exhibits a switching energy of 2.6 pJ per bit. Furthermore, guided by our device-circuit modelling, we propose vertically stacked channel FETs for high-density sub-0.01 μm2 memory cells, offering a new beyond-Si solution to enable 3-D embedded memories for future computing systems. Designing efficient, scalable and low-thermal-budget 2D Materials for 3D integration remains a challenge. Here, the authors report the development of a hybrid-(solution-processed-exfoliated) integration of 2D Material based 1T1R which uses a multilayer WSe2 p-FET and a multilayer printed WSe2 RRAM.

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All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration.

Untethered computing using deep convolutional neural networks (DCNNs) at the edge of IoT with limited resources requires systems that are exceedingly power and area-efficient. Analog in-memory matrix-matrix multiplications enabled by emerging memories can significantly reduce the energy budget of such systems and result in compact accelerators. In this article, we report a high-throughput RRAM-based DCNN processor that boasts $7.12\mathbf {\times }$ area-efficiency (AE) and $6.52\mathbf {\times }$ power-efficiency (PE) enhancements over state-of-the-art accelerators. We achieve this by coupling a novel in-memory computing methodology with a staggered-3D memristor array. Our variation-tolerant in-memory compute method, which performs operations on signed floating-point numbers within a single array, leverages charge domain operations and conductance discretization to reduce peripheral overheads. Voltage pulses applied at the staggered bottom electrodes of the 3D-array generate a concurrent input shift and parallelize convolution operations to boost throughput. The high density and low footprint of the 3D-array, along with the modified in-memory M2M execution, improve peak AE to 9.1TOPsmm−2 while the elimination of input regeneration improves PE to 10.6TOPsW−1. This work provides a path towards infallible RRAM-based hardware accelerators that are fast, low power, and low area.

High-Throughput, Area-Efficient, and Variation-Tolerant 3-D In-Memory Compute System for Deep Convolutional Neural Networks

In this work, we demonstrate the first fully printed WSe 2 resistive random access memory (RRAM) fabricated using aerosol jet printing approach from few layers WSe 2 suspended solution at room temperature on flexible kapton substrate. The printed WSe 2 RRAM exhibits forming free, unipolar behaviour, sub 1-V switching voltage, 2 orders high resistance state (HRS)/low resistance state (LRS) ratio, and large LRS retention time > 2.5 hours. Furthermore, the WSe 2 RRAM exhibits both volatile and non-volatile switching behaviour with a transition set current of 2 µA. In addition, the WSe 2 RRAM retains its functionality even after flexing down to a bending-radii of 5 cm, thus showing suitability for its use as embedded memory in conformal electronics system.

Aerosol Jet Printed WSe 2 Based RRAM on Kapton Suitable for Flexible Monolithic Memory Integration

In this paper, we discuss the DTCO of two disruptive emerging device technologies; Vertical gate-all-around FETs and embedded monolithic 3D (ITIR) integration of 2D material-based resistive RAM and switch transistors. We showed that VFET has the potential for lower parasitics and improved SRAM performance. In the case of the 2D material-based ITIR, we show that stacking of nanosheets and reduction of set current is necessary to scale the cell below 0.1$\mu m^{2}$ cell sizes.

Design-Technology Co-optimization (DTCO) for Emerging Disruptive Logic & Embedded Memory Process Technologies

In this paper, we study the implementation of a SiO x ReRAM an artificial spiking neuron network (SNN) as a memristive synapse. The analog switching SiO x based resistive random access memory (ReRAM) uses room temperature process and switches at sub 1.2V, suitable for BEOL integration. We analyze the neuron circuit speed impact from ReRAM switching, supply voltage and power consumption. With an single industry I/O voltage of +1.8V besides necessary negative supply for bipolar signal generation, and by co-optimizing the neuron circuit in the region of μs, the operating speed can be 3 orders faster than existing reported SNN circuit. In addition, we show that the ReRAM switching time poses the speed bottleneck for the SNN circuit. In order to further enhance the SNN operating speed, improvement to the ReRAM switching time is needed, or the need to increase the voltage supply but at the expense of power consumption.

Jessie Xuhua Niu

Papers

All WSe2 1T1R resistive RAM cell for future monolithic 3D embedded memory integration.

High-Throughput, Area-Efficient, and Variation-Tolerant 3-D In-Memory Compute System for Deep Convolutional Neural Networks

Aerosol Jet Printed WSe 2 Based RRAM on Kapton Suitable for Flexible Monolithic Memory Integration

Design-Technology Co-optimization (DTCO) for Emerging Disruptive Logic & Embedded Memory Process Technologies

Design and Study of an Artificial Spiking Neuron Enabled by Low-Voltage SiOx-based ReRAM