This paper mainly focuses on the development of the NOR flash memory technology, with the aim of describing both the basic functionality of the memory cell used so far and the main cell architecture consolidated today. The NOR cell is basically a floating-gate MOS transistor, programmed by channel hot electron and erased by Fowler-Nordheim tunneling. The main reliability issues, such as charge retention and endurance, are discussed, together with an understanding of the basic physical mechanisms responsible. Most of these considerations are also valid for the NAND cell, since it is based on the same concept of floating-gate MOS transistor. Furthermore, an insight into the multilevel approach, where two bits are stored in the same cell, is presented. In fact, the exploitation of the multilevel approach at each technology node allows an increase of the memory efficiency, almost doubling the density at the same chip size, enlarging the application range and reducing the cost per bit. Finally, NOR flash cell scaling issues are covered, pointing out the main challenges. Flash cell scaling has been demonstrated to be really possible and to be able to follow Moore's law down to the 130-nm technology generations. Technology development and consolidated know-how is expected to sustain the scaling trend down to 90- and 65-nm technology nodes. One of the crucial issues to be solved to allow cell scaling below the 65-nm node is the tunnel oxide thickness reduction, as tunnel thinning is limited by intrinsic and extrinsic mechanisms.

Introduction to flash memory

Nonvolatile memory technologies in Si-based electronics date back to the 1990s. Ferroelectric field-effect transistor (FeFET) was one of the most promising devices replacing the conventional Flash memory facing physical scaling limitations at those times. A variant of charge storage memory referred to as Flash memory is widely used in consumer electronic products such as cell phones and music players while NAND Flash-based solid-state disks (SSDs) are increasingly displacing hard disk drives as the primary storage device in laptops, desktops, and even data centers. The integration limit of Flash memories is approaching, and many new types of memory to replace conventional Flash memories have been proposed. Emerging memory technologies promise new memories to store more data at less cost than the expensive-to-build silicon chips used by popular consumer gadgets including digital cameras, cell phones and portable music players. They are being investigated and lead to the future as potential alternatives to existing memories in future computing systems. Emerging nonvolatile memory technologies such as magnetic random-access memory (MRAM), spin-transfer torque random-access memory (STT-RAM), ferroelectric random-access memory (FeRAM), phase-change memory (PCM), and resistive random-access memory (RRAM) combine the speed of static random-access memory (SRAM), the density of dynamic random-access memory (DRAM), and the nonvolatility of Flash memory and so become very attractive as another possibility for future memory hierarchies. Many other new classes of emerging memory technologies such as transparent and plastic, three-dimensional (3-D), and quantum dot memory technologies have also gained tremendous popularity in recent years. Subsequently, not an exaggeration to say that computer memory could soon earn the ultimate commercial validation for commercial scale-up and production the cheap plastic knockoff. Therefore, this review is devoted to the rapidly developing new class of memory technologies and scaling of scientific procedures based on an investigation of recent progress in advanced Flash memory devices.

/pdf/overview-of-emerging-nonvolatile-memory-technologies-1j483ed6lr.pdf

Overview of emerging nonvolatile memory technologies

We present a device structure of SiO2∕SiN∕Al2O3 (SANOS). The use of a high-k dielectric material, specially Al2O3, in the blocking oxide concentrates the electric fields across the tunnel oxide and SiN, and releases it across the blocking oxide under program and erase mode. This effect leads to lower program and erase voltage as well as faster erase speed than the conventional SiO2∕SiN∕SiO2 (SONOS) device. Moreover, it is shown that the fast erase operation is performed even at a thicker tunnel oxide over 30A where the hole direct tunneling current through the tunnel oxide is reduced significantly and thus the SANOS device has the excellent bake retention.

Charge-trapping device structure of SiO2∕SiN∕high-k dielectric Al2O3 for high-density flash memory

An array of memory cells configured to store at least one bit per one F 2 includes substantially vertical structures providing an electronic memory function spaced apart a distance equal to one half of a minimum pitch of the array. The structures providing the electronic memory function are configured to store more than one bit per gate. The array also includes electrical contacts to the memory cells including the substantially vertical structures. The cells can be programmed to have one of a number of charge levels trapped in the gate insulator adjacent to the first source/drain region such that the channel region has a first voltage threshold region (Vt 1 ) and a second voltage threshold region (Vt 2 ) and such that the programmed cell operates at reduced drain source current.

NROM memory cell, memory array, related devices and methods

Structures and methods for vertical memory cell. The vertical memory cell includes a vertical metal oxide semiconductor field effect transistor (MOSFET) extending outwardly from a substrate. The MOSFET has a first source/drain region, a second source/drain region, a channel region between the first and the second source/drain regions, and a gate separated from the channel region by a gate insulator. A first transmission line is coupled to the first source/drain region. A second transmission line is coupled to the second source/drain region. The MOSFET is adapted to be programmed to have a charge trapped in at least one of a first storage region and a second storage region in the gate insulator and operated with either the first source/drain region or the second source/drain region serving as the source region.

Vertical NROM having a storage density of 1 bit per 1F2

Scaling the programming voltage, while still maintaining 10-year data retention time, has always been a big challenge for polysilicon–oxide–nitride–oxide–silicon (SONOS) researchers. We describe progress in the design and scaling of SONOS nonvolatile memory devices. We have realized −9+10 V (1 ms) programmable SONOS devices ensuring 10-year retention time after 107 erase/write cycles at 85°C. Deuterium anneals, applied in SONOS device fabrication for the first time, improves the endurance characteristics when compared with traditional hydrogen or forming gas anneals. We introduce scaling considerations and process optimization along with experiments and SONOS device characterization. A field programmable gate array-based measurement system is described for the dynamic characterization of SONOS nonvolatile memory devices.

Design considerations in scaled SONOS nonvolatile memory devices

Polysilicon-oxide–nitride–oxide–silicon nonvolatile memory devices are characterized by a high concentration of traps in the silicon nitride layer with a well-defined trapping distance, corresponding to the tunnel oxide thickness. A “breakpoint” is observed at a particular frequency with an inverse equivalent to the trap-to-trap tunneling time constant by variable frequency charge pumping technique, from which the tunnel oxide thickness can be decided. By examining the charge transport and trapping properties of nitride films utilizing charge separation technique, an experimental method to extract the silicon nitride storage layer thickness has been developed. Excellent agreement is obtained between the ellipsometry results and extracted values.

Electrical characterization of ONO triple dielectric in SONOS nonvolatile memory devices

We describe progress in the design and scaling of SONOS nonvolatile memory devices. The deterioration of the Si-SiO/sub 2/ interface is associated with the degradation of long term retention in SONOS nonvolatile semiconductor memory (NVSM) devices. Two-step, high temperature deuterium anneals improves the endurance characteristics and retention reliability over traditional hydrogen anneals. We have realized -9 V +10 V (1ms) programmable SONOS devices ensuring 10 years retention time after 10/sup 7/ erase/write cycles at 85/spl deg/C. We introduce scaling considerations and process optimization along with experiments and SONOS device characterization. An FPGA-based measurement system is described for the dynamic characterization of SONOS nonvolatile memory devices.

Jiankang Bu

Papers

Design considerations in scaled SONOS nonvolatile memory devices

Electrical characterization of ONO triple dielectric in SONOS nonvolatile memory devices

Retention reliability enhanced SONOS NVSM with scaled programming voltage