An RF-DC power conversion system is designed to efficiently convert far-field RF energy to DC voltages at very low received power and voltages. Passive rectifier circuits are designed in a 0.25 mum CMOS technology using floating gate transistors as rectifying diodes. The 36-stage rectifier can rectify input voltages as low as 50 mV with a voltage gain of 6.4 and operates with received power as low as 5.5 muW(22.6 dBm). Optimized for far field, the circuit operates at a distance of 44 m from a 4 W EIRP source. The high voltage range achieved at low load current make it ideal for use in passively powered sensor networks.

Efficient Far-Field Radio Frequency Energy Harvesting for Passively Powered Sensor Networks

The last two decades have witnessed several advances in microfabrication technologies and electronics, leading to the development of small, low-power devices for wireless sensing, data transmission, actuation, and medical implants. Unfortunately, the actual implementation of such devices in their respective environment has been hindered by the lack of scalable energy sources that are necessary to power and maintain them. Batteries, which remain the most commonly used power sources, have not kept pace with the demands of these devices, especially in terms of energy density. In light of this challenge, the concept of vibratory energy harvesting has flourished in recent years as a possible alternative to provide a continuous power supply. While linear vibratory energy harvesters have received the majority of the literature’s attention, a significant body of the current research activity is focused on the concept of purposeful inclusion of nonlinearities for broadband transduction. When compared to their linear resonant counterparts, nonlinear energy harvesters have a wider steady-state frequency bandwidth, leading to a common belief that they can be utilized to improve performance in ambient environments. Through a review of the open literature, this paper highlights the role of nonlinearities in the transduction of energy harvesters under different types of excitations and investigates the conditions, in terms of excitation nature and potential shape, under which such nonlinearities can be beneficial for energy harvesting. [DOI: 10.1115/1.4026278]

On the Role of Nonlinearities in Vibratory Energy Harvesting: A Critical Review and Discussion

RF energy harvesting holds a promise able future for generating a small amount of electrical power to drive partial circuits in wirelessly communicating electronics devices. This paper presents the overview and progress achieved in RF energy harvesting field. A modified form of existing CMOS based voltage doubler circuit is presented to achieve 160% increase in output power over traditional circuits at 0 dBm input power. A schottky diode based RF energy harvesting circuit performance is also studied with practical and simulations results.

RF energy harvesting system and circuits for charging of mobile devices

Neural implants have emerged over the last decade as highly effective solutions for the treatment of dysfunctions and disorders of the nervous system. These implants establish a direct, often bidirectional, interface to the nervous system, both sensing neural signals and providing therapeutic treatments. As a result of the technological progress and successful clinical demonstrations, completely implantable solutions have become a reality and are now commercially available for the treatment of various functional disorders. Central to this development is the wireless power transfer (WPT) that has enabled implantable medical devices (IMDs) to function for extended durations in mobile subjects. In this review, we present the theory, link design, and challenges, along with their probable solutions for the traditional near-field resonant inductively coupled WPT, capacitively coupled short-ranged WPT, and more recently developed ultrasonic, mid-field, and far-field coupled WPT technologies for implantable applications. A comparison of various power transfer methods based on their power budgets and WPT range follows. Power requirements of specific implants like cochlear, retinal, cortical, and peripheral are also considered and currently available IMD solutions are discussed. Patient's safety concerns with respect to electrical, biological, physical, electromagnetic interference, and cyber security from an implanted neurotech device are also explored in this review. Finally, we discuss and anticipate future developments that will enhance the capabilities of current-day wirelessly powered implants and make them more efficient and integrable with other electronic components in IMDs.

Wireless Power Transfer Strategies for Implantable Bioelectronics

A system, method, and computer program product are provided for a touch or pressure signal-based interface. In operation, a touch or pressure signal is received in association with a touch interface of a device. To this end, a user experience is altered utilizing the signal. A system, method, and computer program product are provided for modifying one or more objects in one or more memory devices. In one embodiment, an apparatus is provided, comprising one or more memory devices including a non-volatile memory. Additionally, the apparatus comprises circuitry including a first communication path for communicating with the at least one processor, and a second communication path for communicating with at least one storage sub-system which operates slower than the one or more memory devices. Further, the circuitry is operable to modify one or more objects in the one or more memory devices.

User interface system, method, and computer program product

This paper presents a RF to DC conversion model for multi-stage rectifiers in UHF RFID transponders. An equation relating the RF power available from the antenna to the DC output voltage produced by a multi-stage rectifier is presented. The proposed model includes effects of the nonlinear forward voltage drop in diodes and impedance matching conditions of the antenna to rectifier interface. Fundamental frequency impedance approximation is used to analyze the resistance of rectifying diodes; parasitic resistive loss components are also included in the analysis of rectifier input resistance. The closed form equation shows insights into design parameter tradeoffs, such as power available from the antenna, antenna radiation resistance, the number of diodes, DC load current, parasitic resistive loss components, diode and capacitor sizes, and frequency of operation. Therefore, it enables the optimization of rectifier parameters for impedance matching with a low-cost printed antenna and shunt tuning inductor, in order to improve the RF to DC conversion efficiency and the operational distance of UHF RFID transponders. Three diode doublers and three multistage rectifiers were fabricated in a 130 nm CMOS process with custom no-mask added Schottky diodes. Measurements of the test IC are in good agreement with the proposed model.

A RF to DC Voltage Conversion Model for Multi-Stage Rectifiers in UHF RFID Transponders

The article first discusses the major non-ideal issues of low-cost transmission media for over Gbps data transmissions - the frequency dispersion loss and channel noise. The former causes ISI in received signal, which presents difficulty for clock and data recovery at high frequencies and results higher BER. The latter further degrades the received signal quality and further limits the data transmission rate and transmission distance. Then, two equalization approaches - transmitter pre-emphasis and receiver equalization, are reviewed, in addition to various adaptation criteria and algorithms.

Equalization in high-speed communication systems

This paper presents a multi-MHz buck regulator for portable applications using an auto-selectable peak- and valley-current control (ASPVCC) scheme. The proposed ASPVCC scheme can enable the current-mode buck regulator to reduce the settling-time requirement of the current sensing by two times. In addition, the dynamically biased shunt feedback technique is employed to improve the sensing speed and the sensing accuracy of both the peak and valley current sensors. With both ASPVCC scheme and advanced current sensors, the buck regulator can thus operate at high switching frequencies with a wide range of duty ratios for reducing the required off-chip inductance. The proposed current-mode buck regulator was fabricated in a standard 0.35-μm CMOS process and occupies a small chip area of 0.54 mm2. Measurement results show that the buck regulator can deliver a maximum output current of 500 mA, operate at 5 MHz with a wide duty-ratio range of about 0.6, use a small-value off-chip inductor of 1 μH, and achieve the peak power efficiency of 91%.

A 5-MHz 91% Peak-Power-Efficiency Buck Regulator With Auto-Selectable Peak- and Valley-Current Control

A fully integrated CMOS impulse generator was designed as a part of the System-on-Chip (SOC) implementation of an Ultra-Wide-Bandwidth (UWB) wireless communication system. Three interpolation delay blocks in series and an XOR block are utilized for the pulse generation. The Gaussian Mono-pulse is generated with a RLC Band-Pass Filter (BPF), and a substrate RF inductor is utilized to avoid using off-chip components. The ideal BPF and the substrate BPF simulation results were compared to predict the actual performance of the impulse generator. The substrate BPF brings wider -3 dB bandwidth (BW), less ripple ratio, and smaller output amplitude. It operates with a center frequency of 3.27 GHz and a -3 dB BW of 3.34 GHz with an inductor value of 10 nH. The impulse generator was designed with MOS current mode logic (MCML) in the TSMC 0.18 /spl mu/m CMOS process.

A CMOS impulse generator for UWB wireless communication systems

This paper presents an adaptive finite impulse response (FIR) equalizer with continuous-time wide-bandwidth delay line in CMOS 0.25-mum process for 2.5-Gb/s to 3.5-Gb/s data communications. To achieve wide bandwidth, fractionally spaced structure is used and an inverter with active-inductor load design is proposed as the delay cell of the tap delay line. Close loop adaptation of the fractionally spaced FIR equalizer is demonstrated using a low-power and area-efficient pulse extraction method as on-chip error detector. Measurement results show that the proposed adaptive equalizer achieves over 75% horizontal eye opening when the channel loss at the half-data-rate frequency varies from 4 dB to 21 dB at 2.5-Gb/s data rate. At 3.5-Gb/s data rate, the equalizer achieves 68% horizontal eye opening when the channel loss is about 9.3 dB at the half-data-rate frequency. The adaptive equalizer including the FIR filter and the error detector occupies 0.095 mm2 die area and dissipates 95 mW at 2.5-Gb/s data rate from 2.5-V voltage supply

Jin Liu

Papers

A RF to DC Voltage Conversion Model for Multi-Stage Rectifiers in UHF RFID Transponders

Equalization in high-speed communication systems

A 5-MHz 91% Peak-Power-Efficiency Buck Regulator With Auto-Selectable Peak- and Valley-Current Control

A CMOS impulse generator for UWB wireless communication systems

A 2.5- to 3.5-Gb/s Adaptive FIR Equalizer With Continuous-Time Wide-Bandwidth Delay Line in 0.25- $muhbox m$ CMOS