Showing papers in "IEEE Journal of Solid-state Circuits in 2011"
TL;DR: The biomimetic CMOS dynamic vision and image sensor described in this paper is based on a QVGA array of fully autonomous pixels containing event-based change detection and pulse-width-modulation imaging circuitry, which ideally results in lossless video compression through complete temporal redundancy suppression at the pixel level.
Abstract: The biomimetic CMOS dynamic vision and image sensor described in this paper is based on a QVGA (304×240) array of fully autonomous pixels containing event-based change detection and pulse-width-modulation (PWM) imaging circuitry. Exposure measurements are initiated and carried out locally by the individual pixel that has detected a change of brightness in its field-of-view. Pixels do not rely on external timing signals and independently and asynchronously request access to an (asynchronous arbitrated) output channel when they have new grayscale values to communicate. Pixels that are not stimulated visually do not produce output. The visual information acquired from the scene, temporal contrast and grayscale data, are communicated in the form of asynchronous address-events (AER), with the grayscale values being encoded in inter-event intervals. The pixel-autonomous and massively parallel operation ideally results in lossless video compression through complete temporal redundancy suppression at the pixel level. Compression factors depend on scene activity and peak at ~1000 for static scenes. Due to the time-based encoding of the illumination information, very high dynamic range - intra-scene DR of 143 dB static and 125 dB at 30 fps equivalent temporal resolution - is achieved. A novel time-domain correlated double sampling (TCDS) method yields array FPN of 56 dB (9.3 bit) for >10 Lx illuminance.
632 citations
TL;DR: A multi-core processor that integrates 48 cores, 4 DDR3 memory channels, and a voltage regulator controller in a 64 2D-mesh network-on-chip architecture that uses message passing while exploiting 384 KB of on-die shared memory for fine grain power management.
Abstract: This paper describes a multi-core processor that integrates 48 cores, 4 DDR3 memory channels, and a voltage regulator controller in a 64 2D-mesh network-on-chip architecture. Located at each mesh node is a five-port virtual cut-through packet-switched router shared between two IA-32 cores. Core-to-core communication uses message passing while exploiting 384 KB of on-die shared memory. Fine grain power management takes advantage of 8 voltage and 28 frequency islands to allow independent DVFS of cores and mesh. At the nominal 1.1 V supply, the cores operate at 1 GHz while the 2D-mesh operates at 2 GHz. As performance and voltage scales, the processor dissipates between 25 W and 125 W. The processor is implemented in 45 nm Hi-K CMOS and has 1.3 billion transistors.
415 citations
TL;DR: Circuit design methods are proposed to enable simplified gate drivers while supporting multiple topologies (and hence output voltages) and verified by a proof-of-concept converter prototype implemented in 0.374 mm2 of a 32 nm SOI process.
Abstract: This paper describes design techniques to maximize the efficiency and power density of fully integrated switched-capacitor (SC) DC-DC converters. Circuit design methods are proposed to enable simplified gate drivers while supporting multiple topologies (and hence output voltages). These methods are verified by a proof-of-concept converter prototype implemented in 0.374 mm2 of a 32 nm SOI process. The 32-phase interleaved converter can be configured into three topologies to support output voltages of 0.5 V-1.2 V from a 2 V input supply, and achieves 79.76% efficiency at an output power density of 0.86 W/mm2 .
407 citations
TL;DR: A systematic approach to designing high frequency and high power oscillators using activity condition is introduced, and a novel triple-push structure is introduced to realize 256 GHz and 482 GHz oscillators.
Abstract: A systematic approach to designing high frequency and high power oscillators using activity condition is introduced. This method finds the best topology to achieve frequencies close to the fmax of the transistors. It also determines the maximum frequency of oscillation for a fixed circuit topology, considering the quality factor of the passive components. Using this technique, in a 0.13 μm CMOS process, we design and implement 121 GHz and 104 GHz fundamental oscillators with the output power of -3.5 dBm and -2.7 dBm, respectively. Next, we introduce a novel triple-push structure to realize 256 GHz and 482 GHz oscillators. The 256 GHz oscillator was implemented in a 0.13 μm CMOS process and the output power of -17 dBm was measured. The 482 GHz oscillator generates -7.9 dBm (0.16 mW) in a 65 nm CMOS process.
347 citations
TL;DR: A low-power precision instrumentation amplifier intended for use in wireless sensor nodes that employs a capacitively-coupled chopper topology to achieve a rail-to-rail input common-mode range as well as high power efficiency and bio-potential sensing.
Abstract: This paper presents a low-power precision instrumentation amplifier intended for use in wireless sensor nodes. It employs a capacitively-coupled chopper topology to achieve a rail-to-rail input common-mode range as well as high power efficiency. A positive feedback loop is employed to boost its input impedance, while a ripple reduction loop suppresses the chopping ripple. To facilitate bio-potential sensing, an optional DC servo loop may be employed to suppress electrode offset. The IA achieves 1 μV offset, 0.16% gain inaccuracy, 134 dB CMRR, 120 dB PSRR and a noise efficiency factor of 3.3. The instrumentation amplifier was implemented in a 65 nm CMOS technology. It occupies only 0.1 mm2 chip area (0.2 mm2 with the DC servo loop) and consumes 1.8 μA current (2.1 μA with the DC servo loop) from a 1 V supply.
314 citations
TL;DR: The fully dynamic design, which is optimized for low-leakage, leads to a standby power consumption of 6 nW and the energy efficiency of this converter can be maintained down to very low sampling rates.
Abstract: This paper presents an asynchronous SAR ADC for flexible, low energy radios. To achieve excellent power efficiency for a relatively moderate resolution, various techniques are introduced to reduce the power consumption: custom-designed 0.5 fF unit capacitors minimize the analog power consumption while asynchronous dynamic logic minimizes the digital power consumption. The variability of the custom-designed capacitors is estimated by a specialized CAD tool and verified by chip measurements. An implemented 8-bit prototype in a 90 nm CMOS technology occupies 228 μm × 240 μm including decoupling capacitors, and achieves an ENOB of 7.77 bit at a sampling frequency of 10.24 MS/s. The power consumption equals 26.3 μW from a 1 V supply, thus resulting in an energy efficiency of 12 fJ/conversion-step. Moreover, the fully dynamic design, which is optimized for low-leakage, leads to a standby power consumption of 6 nW. In that way, the energy efficiency of this converter can be maintained down to very low sampling rates.
311 citations
TL;DR: This paper proposes a low-complexity minimum mean-squared error (MMSE) based parallel interference cancellation algorithm, develops a suitable VLSI architecture, and presents a corresponding four-stream 1.5 mm2 detector chip in 90 nm CMOS technology, which is the first ASIC implementation of a SISO detector for iterative MIMO decoding.
Abstract: Multiple-input multiple-output (MIMO) technology is the key to meet the demands for data rate and link reliability of modern wireless communication systems, such as IEEE 802.11n or 3GPP-LTE. The full potential of MIMO systems can, however, only be achieved by means iterative MIMO decoding relying on soft-input soft-output (SISO) data detection. In this paper, we describe the first ASIC implementation of a SISO detector for iterative MIMO decoding. To this end, we propose a low-complexity minimum mean-squared error (MMSE) based parallel interference cancellation algorithm, develop a suitable VLSI architecture, and present a corresponding four-stream 1.5 mm2 detector chip in 90 nm CMOS technology. The fabricated ASIC includes all necessary preprocessing circuitry and exceeds the 600 Mb/s peak data-rate of IEEE 802.11n. A comparison with state-of-the-art MIMO-detector implementations demonstrates the performance benefits of our ASIC prototype in practical system-scenarios.
297 citations
TL;DR: An efficient energy harvester for RF-powered sensor networks is presented, based on an improved multi-stage rectifier, which exploits a fully passive threshold self-compensation scheme to overcome the limitation due to the input dead zone.
Abstract: This paper presents an efficient energy harvester for RF-powered sensor networks. The circuit is based on an improved multi-stage rectifier, which exploits a fully passive threshold self-compensation scheme to overcome the limitation due to the input dead zone. A CAD-oriented design methodology is also proposed, which is aimed at maximizing the overall power conversion efficiency of the harvester through an optimum trade-off among matching losses, power reflection and rectifier efficiency. According to the proposed methodology, a 915-MHz harvester comprising an integrated input matching network and a 17-stage self-compensated rectifier has been designed and fabricated in a 90-nm CMOS technology. The rectifier exhibits a remarkably low input power threshold, as it is able to deliver a 1-V dc output voltage to a capacitive load with a very small input power of -24 dBm (4 μW). When driving a 1-MΩ load, the device can supply a 1.2-V output with an input power of -18.8 dBm (13.1 μW). The achieved results exceed the performance of previously reported RF multi-stage rectifiers in standard analog CMOS technology.
271 citations
TL;DR: While core min-delay constraints limit the potential benefits of the embedded EDS design, a salient advantage of the TRC design is the ability to detect a wider range of dynamic delay variation, as demonstrated through low supply voltage (VCC) measurements.
Abstract: A 45 nm microprocessor core integrates resilient error-detection and recovery circuits to mitigate the clock frequency (FCLK) guardbands for dynamic parameter variations to improve throughput and energy efficiency. The core supports two distinct error-detection designs, allowing a direct comparison of the relative trade-offs. The first design embeds error-detection sequential (EDS) circuits in critical paths to detect late timing transitions. In addition to reducing the Fclk guardbands for dynamic variations, the embedded EDS design can exploit path-activation rates to operate the microprocessor faster than infrequently-activated critical paths. The second error-detection design offers a less-intrusive approach for dynamic timing-error detection by placing a tunable replica circuit (TRC) per pipeline stage to monitor worst-case delays. Although the TRCs require a delay guardband to ensure the TRC delay is always slower than critical-path delays, the TRC design captures most of the benefits from the embedded EDS design with less implementation overhead. Furthermore, while core min-delay constraints limit the potential benefits of the embedded EDS design, a salient advantage of the TRC design is the ability to detect a wider range of dynamic delay variation, as demonstrated through low supply voltage (VCC) measurements. Both error-detection designs interface with error-recovery techniques, enabling the detection and correction of timing errors from fast-changing variations such as high-frequency VCC droops. The microprocessor core also supports two separate error-recovery techniques to guarantee correct execution even if dynamic variations persist. The first technique requires clock control to replay errant instructions at 1/2FCLK. In comparison, the second technique is a new multiple-issue instruction replay design that corrects errant instructions with a lower performance penalty and without requiring clock control. Silicon measurements demonstrate that resilient circuits enable a 41% throughput gain at equal energy or a 22% energy reduction at equal throughput, as compared to a conventional design when executing a benchmark program with a 10% VCC droop. In addition, the microprocessor includes a new adaptive clock control circuit that interfaces with the resilient circuits and a phase-locked loop (PLL) to track recovery cycles and adapt to persistent errors by dynamically changing Fclk f°Γ maximum efficiency.
263 citations
TL;DR: A voltage reference circuit operating with all transistors biased in weak inversion, providing a mean reference voltage of 257.5 mV, has been fabricated in 0.18 m CMOS technology with accurate subthreshold design.
Abstract: A voltage reference circuit operating with all transistors biased in weak inversion, providing a mean reference voltage of 257.5 mV, has been fabricated in 0.18 m CMOS technology. The reference voltage can be approximated by the difference of transistor threshold voltages at room temperature. Accurate subthreshold design allows the circuit to work at room temperature with supply voltages down to 0.45 V and an average current consumption of 5.8 nA. Measurements performed over a set of 40 samples showed an average temperature coefficient of 165 ppm/ C with a standard deviation of 100 ppm/ C, in a temperature range from 0 to 125°C. The mean line sensitivity is ≈0.44%/V, for supply voltages ranging from 0.45 to 1.8 V. The power supply rejection ratio measured at 30 Hz and simulated at 10 MHz is lower than -40 dB and -12 dB, respectively. The active area of the circuit is ≈0.043mm2.
254 citations
TL;DR: A 12-GS/s 5-bit time-interleaved flash ADC is realized in 65-nm CMOS to improve dynamic performance, and comparator offset calibration to reduce power dissipation.
Abstract: This paper presents a 12-GS/s 5-bit time-interleaved flash ADC realized in 65-nm CMOS. To improve the dynamic performance at high input frequencies, a statistics-based background calibration scheme for timing skew is employed. The timing skew is detected in the digital domain through a correlation-based algorithm and minimized by adjusting digitally controlled delay lines. In order to minimize power consumption, we employ near minimum size comparators, whose offset is reduced through foreground calibrated trim-DAC circuitry. With the timing calibration activated, the skew-related impairments are reduced by 12 dB at high input frequencies, resulting in an SNDR of 25.1 dB near Nyquist. The prototype IC consumes 81 mW from a 1.1 V supply, yielding a figure-of-merit of 0.35 pJ/conversion-step at low input frequencies, and 0.46 pJ/conversion-step for inputs near Nyquist.
TL;DR: The design and implementation of an analog signal processor (ASP) ASIC for portable ECG monitoring systems and the proposed continuous-time electrode-tissue impedance monitoring circuit enables the monitoring of the signal integrity.
Abstract: This paper presents the design and implementation of an analog signal processor (ASP) ASIC for portable ECG monitoring systems The ASP ASIC performs four major functionalities: 1) ECG signal extraction with high resolution, 2) ECG signal feature extraction, 3) adaptive sampling ADC for the compression of ECG signals, 4) continuous-time electrode-tissue impedance monitoring for signal integrity monitoring These functionalities enable the development of wireless ECG monitoring systems that have significantly lower power consumption yet that are more capable than their predecessors The ASP has been implemented in 05 μm CMOS process and consumes 30 μW from a 2 V supply The noise density of the ECG readout channel is 85 nV/√Hz and the CMRR is better that 105 dB The adaptive sampling ADC is capable of compressing the ECG data by a factor of 7 and the heterodyne chopper readout extracts the features of the ECG signals Combination of these two features leads to a factor 4 reduction in the power consumption of a wireless ECG monitoring system Furthermore, the proposed continuous-time impedance monitoring circuit enables the monitoring of the signal integrity
TL;DR: A fully integrated switched-capacitor power amplifier that operates on the envelope of a nonconstant envelope modulated signal as an RF-DAC in an EER/Polar architecture to amplify the signal efficiently.
Abstract: A fully integrated switched-capacitor power amplifier (SCPA) utilizes switched-capacitor techniques in an EER/Polar architecture. It operates on the envelope of a nonconstant envelope modulated signal as an RF-DAC in order to amplify the signal efficiently. The measured maximum output power and PAE are 25.2 dBm and 45%, respectively. When amplifying an 802.11g 64-QAM orthogonal frequency-division multiplexing (OFDM) signal, the measured error vector magnitude is 2.6% and the average output power and power-added efficiencies are 17.7 dBm and 27%, respectively.
TL;DR: In this article, a two-stage pipeline ADC architecture with a large first-stage resolution, enabled with the help of a SAR-based sub-ADC, is presented, achieving an ENOB of 104b at Nyquist and a figure-of-merit of 52 f J/conversion-step.
Abstract: Successive approximation register (SAR) ADC architectures are popular for achieving high energy efficiency but they suffer from resolution and speed limitations On the other hand pipeline ADC architectures can achieve high resolution and speed but have lower energy-efficiency and are more complex We pro pose a two-stage pipeline ADC architecture with a large first-stage resolution, enabled with the help of a SAR-based sub-ADC The prototype 12b 50 MS/s ADC achieves an ENOB of 104b at Nyquist, and a figure-of-merit of 52 f J/conversion-step The ADC achieves low-power, high-resolution and high-speed operation without calibration The ADC is fabricated in 65 nm and 90 nm CMOS and occupies a core area of only 016 mm2
TL;DR: A perturbation-based digital calibration technique is described that closely couples with the architecture choice to accomplish simultaneous identification of multiple capacitor mismatch errors of the ADC, enabling the downsizing of all sampling capacitors to save power and silicon area.
Abstract: This paper presents a sub-radix-2 redundant architecture to improve the performance of switched-capacitor successive-approximation-register (SAR) analog-to-digital converters (ADCs). The redundancy not only guarantees digitally correctable static nonlinearities of the converter, it also offers means to combat dynamic errors in the conversion process, and thus, accelerating the speed of the SAR architecture. A perturbation-based digital calibration technique is also described that closely couples with the architecture choice to accomplish simultaneous identification of multiple capacitor mismatch errors of the ADC, enabling the downsizing of all sampling capacitors to save power and silicon area. A 12-bit prototype measured a Nyquist 70.1-dB signal-to-noise-plus-distortion ratio (SNDR) and a Nyquist 90.3-dB spurious free dynamic range (SFDR) at 22.5 MS/s, while dissipating 3.0-mW power from a 1.2-V supply and occupying 0.06-mm2 silicon area in a 0.13-μm CMOS process. The figure of merit (FoM) of this ADC is 51.3 fJ/step measured at 22.5 MS/s and 36.7 fJ/step at 45 MS/s.
TL;DR: A highly-linear software-defined radio operating from 400 MHz to 6 GHz is presented, with the purpose of removing any dedicated filtering at the antenna thanks to a 2.5 V linear LNA and mixer-based RF blocker filter.
Abstract: A highly-linear software-defined radio operating from 400 MHz to 6 GHz is presented, with the purpose of removing any dedicated filtering at the antenna. Very high resilience to out-of-band interference is achieved thanks to a 2.5 V linear LNA and mixer-based RF blocker filter. The 2 mm2, 40 nm digital CMOS receiver achieves +10 dBm out-of-band IIP3 and >; +70 dBm calibrated IIP2 at 3 dB NF. It tolerates 0 dBm blockers at 20 MHz offset with acceptable blocker NF.
TL;DR: A quad-band 2.5G receiver is designed to replace the front-end SAW filters with on-chip bandpass filters and to integrate the LNA matching components, as well as the RF baluns, to achieve a typical sensitivity of -110 dBm or better, while saving a considerable amount of BOM.
Abstract: A quad-band 2.5G receiver is designed to replace the front-end SAW filters with on-chip bandpass filters and to integrate the LNA matching components, as well as the RF baluns. The receiver achieves a typical sensitivity of -110 dBm or better, while saving a considerable amount of BOM. Utilizing an arrangement of four baseband capacitors and MOS switches driven by 4-phase 25% duty-cycle clocks, high-Q BPF's are realized to attenuate the 0 dBm out-of-band blocker. The 65 nm CMOS SAW-less receiver integrated as a part of a 2.5G SoC, draws 55 mA from the battery, and measures an out-of-band 1 dB-compression of greater than +2 dBm. Measured as a stand-alone, as well as the baseband running in call mode in the platform level, the receiver passes the 3GPP specifications with margin.
TL;DR: The design and implementation aspects of parallel turbo-decoders that reach the 326.4 Mb/s LTE peak data-rate using multiple soft-input soft-output decoder that operate in parallel are addressed.
Abstract: Turbo-decoding for the 3GPP-LTE (Long Term Evolution) wireless communication standard is among the most challenging tasks in terms of computational complexity and power consumption of corresponding cellular devices. This paper addresses design and implementation aspects of parallel turbo-decoders that reach the 326.4 Mb/s LTE peak data-rate using multiple soft-input soft-output decoders that operate in parallel. To highlight the effectiveness of our design-approach, we realized a 3.57 mm2 radix-4based 8× parallel turbo-decoder ASIC in 0.13 μm CMOS technology achieving 390 Mb/s. At the more realistic 100 Mb/s LTE milestone targeted by industry today, the turbo-decoder consumes only 69 mW.
TL;DR: An activity-dependent intracortical microstimulation (ICMS) system-on-chip (SoC) that converts extracellular neural spikes recorded from one brain region to electrical stimuli delivered to another brain region in real time in vivo is described.
Abstract: This paper describes an activity-dependent intracortical microstimulation (ICMS) system-on-chip (SoC) that converts extracellular neural spikes recorded from one brain region to electrical stimuli delivered to another brain region in real time in vivo. The 10.9-mm2 SoC incorporates two identical 4-channel modules, each comprising an analog recording front-end with total input noise voltage of 3.12 μVrms and noise efficiency factor (NEF) of 2.68, 5.9-μW 10-bit successive approximation register analog-to-digital converters (SAR ADCs), 12.4-μW digital spike discrimination processor, and a programmable constant-current microstimulating back-end that delivers up to 94.5 μA with 6-bit resolution to stimulate the cortical tissue when triggered by neural activity. For autonomous operation, the SoC also integrates biasing and clock generation circuitry, frequency-shift-keyed (FSK) transmitter at 433 MHz, and dc-dc converter that generates a power supply of 5.05 V for the microstimulating back-end from a single 1.5-V battery. Measured results from electrical performance characterization and biological experiments with anesthetized rats are presented from a prototype chip fabricated in AMS 0.35 μm two-poly four-metal (2P/4M) CMOS. A noise analysis for the selected low-noise amplifier (LNA) topology is presented that obtains a minimum NEF of 2.33 for a practical design given the technology parameters and power supply voltage. Future considerations in the SoC design with respect to silicon area and power consumption when increasing the number of channels are also discussed.
TL;DR: A 2.1 M pixel, 120 frame/s CMOS image sensor with column-parallel delta-sigma (ΔΣ) ADC architecture with second-order ΔΣ ADC improves the conversion speed while reducing the random noise (RN) level as well.
Abstract: This paper presents a 2.1 M pixel, 120 frame/s CMOS image sensor with column-parallel delta-sigma (ΔΣ) ADC architecture. The use of a second-order ΔΣ ADC improves the conversion speed while reducing the random noise (RN) level as well. The ΔΣ ADC employing an inverter-based ΔΣ modulator and a compact decimation filter is accommodated within a fine pixel pitch of 2.25-μm and improves energy efficiency while providing a high frame-rate of 120 frame/s. A prototype image sensor has been fabricated with a 0.13-μm CMOS process. Measurement results show a RN of 2.4 erms- and a dynamic range of 73 dB. The power consumption of the prototype image sensor is only 180 mW. This work achieves the energy efficiency of 1.7 e-·nJ.
TL;DR: The ability of the sensor to capture very fast moving objects, rotating at 10 K revolutions per second, has been verified experimentally and a compact preamplification stage has been introduced that allows to improve the minimum detectable contrast over previous designs.
Abstract: This paper presents a 128 × 128 dynamic vision sensor. Each pixel detects temporal changes in the local illumination. A minimum illumination temporal contrast of 10% can be detected. A compact preamplification stage has been introduced that allows to improve the minimum detectable contrast over previous designs, while at the same time reducing the pixel area by 1/3. The pixel responds to illumination changes in less than 3.6 μs. The ability of the sensor to capture very fast moving objects, rotating at 10 K revolutions per second, has been verified experimentally. A frame-based sensor capable to achieve this, would require at least 100 K frames per second.
TL;DR: A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area.
Abstract: This work presents measured results from test chips containing circuits implemented with micro-electro-mechanical (MEM) relays. The relay circuits designed on these test chips illustrate a range of important functions necessary for the implementation of integrated VLSI systems and lend insight into circuit design techniques optimized for the physical properties of these devices. To explore these techniques a hybrid electro-mechanical model of the relays' electrical and mechanical characteristics has been developed, correlated to measurements, and then also applied to predict MEM relay performance if the technology were scaled to a 90 nm technology node. A theoretical, scaled, 32-bit MEM relay-based adder, with a single-bit functionality demonstrated by the measured circuits, is found to offer a factor of ten energy efficiency gain over an optimized CMOS adder for sub-20 MOPS throughputs at a moderate increase in area.
TL;DR: An embedded processor platform chip using an ARM Cortex-M3 suitable for mapping medical applications requiring microwatt power consumption is presented and the first sub-microwatt per channel electroencephalograph (EEG) seizure detection is demonstrated.
Abstract: Battery life specifications drive the power consumption requirements of integrated circuits in implantable, wearable, and portable medical devices. In this paper, we present an embedded processor platform chip using an ARM Cortex-M3 suitable for mapping medical applications requiring microwatt power consumption. Ultra-low-power operation is achieved via 0.5-1.0 V operation, a 28 fW/bit fully differential subthreshold 6T SRAM, a 90%-efficient DC-DC converter, and a 100-nJ fast Fourier transform (FFT) accelerator to reduce processor workload. Using a combination of novel circuit design, system architecture, and SoC implementation, the first sub-microwatt per channel electroencephalograph (EEG) seizure detection is demonstrated.
TL;DR: Novel circuits for high-voltage digital level shifting with zero static power consumption and 50% less silicon area are presented, and exhibit a factor of 20-80 lower dynamic power consumption typically.
Abstract: We present novel circuits for high-voltage digital level shifting with zero static power consumption. The conventional topology is analysed, showing the strong dependence of speed and dynamic power on circuit area. Novel techniques are shown to circumvent this and speed up the operation of the conventional level-shifter architecture by a factor of 5-10 typically and 30-190 in the worst case. In addition, these circuits use 50% less silicon area and exhibit a factor of 20-80 lower dynamic power consumption typically. Design guidelines and equations are given to make the design robust over process corners, ensuring good production yield. The circuits were fabricated in a 0.35 high-voltage CMOS process and verified. Due to power and IO speed limitation on the test chip, a special ring oscillator and divider structure was used to measure inherent circuit speed.
TL;DR: By utilizing the detector, a millimeter-wave image is constructed, demonstrating its potential application in millimeters-wave and THz imaging.
Abstract: A 2×2 array of 280-GHz Schottky-barrier diode detectors with an on-chip patch antenna (255 × 250 μm2) is fabricated in a 130-nm logic CMOS process. The series resistance of diode is minimized using poly-gate separation (PGS), and exhibits a cut-off frequency of 2 THz. Each detector unit can detect an incident carrier with 100-Hz ~ 2-MHz amplitude modulation. At 1-MHz modulation frequency, the estimated voltage responsivity and noise equivalent power (NEP) of the detector unit are 250 V/W and 33 pW/Hz1/2, respectively. An integrated low-noise amplifier further boosts the responsivity to 80 kV/W. At supply voltage of 1.2 V, the entire chip consumes 1.6 mW. The array occupies 1.5 × 0.8 mm2. A set of millimeter-wave images with a signal-noise ratio of 48 dB is formed using the detector. These suggest potential utility of Schottky diode detectors fabricated in CMOS for millimeter wave and sub-millimeter wave imaging.
TL;DR: This paper presents a 64-times interleaved 2.6 GS/s 10b successive-approximation-register (SAR) ADC in 65 nm CMOS that combines interleaving hierarchy with an open-loop buffer array operated in feedforward-sampling and feedback-SAR mode.
Abstract: This paper presents a 64-times interleaved 2.6 GS/s 10b successive-approximation-register (SAR) ADC in 65 nm CMOS. The ADC combines interleaving hierarchy with an open-loop buffer array operated in feedforward-sampling and feedback-SAR mode. The sampling front-end consists of four interleaved T/Hs at 650 MS/s that are optimized for timing accuracy and sampling linearity, while the back-end consists of four ADC arrays, each consisting of 16 10b current-mode non-binary SAR ADCs. The interleaving hierarchy allows for many ADCs to be used per T/H and eliminates distortion stemming from open loop buffers interfacing between the front-end and back-end. Startup on-chip calibration deals with offset and gain mismatches as well as DAC linearity. Measurements show that the prototype ADC achieves an SNDR of 48.5 dB and a THD of less than 58 dB at Nyquist with an input signal of 1.4 . An estimated sampling clock skew spread of 400 fs is achieved by careful design and layout. Up to 4 GHz an SNR of more than 49 dB has been measured, enabled by the less than 110 fs rms clock jitter. The ADC consumes 480 mW from 1.2/1.3/1.6 V supplies and occupies an area of 5.1 mm.
TL;DR: Detailed analysis proves the feature of reducing the input-referred noise and offset by simply increasing the number of delay stages by effectively eliminating static power consumption in the proposed time-domain comparator.
Abstract: This paper presents a 100 kS/s, 1.3 μW, 9.3 ENOB successive approximation ADC with a time-domain comparator. The proposed time-domain comparator utilizes a differential multi-stage VCDL, resulting in a highly digital operation eliminating static power consumption. The effects of gain, noise, and offset are also investigated by detailed analysis which proves the feature of reducing the input-referred noise and offset by simply increasing the number of delay stages. For verification, the proposed ADC is fabricated in a 0.18 μm CMOS. With a single supply voltage of 0.6 V, the ADC consumes 1.3 μW at the maximum sampling rate of 100 kS/s. The measured ENOB is 9.3 b showing a figure of merit of 21 f J/conversion-step.
TL;DR: Transistors demonstrate an extrapolated fmax of >;800 GHz while maintaining a common-emitter breakdown voltage (BVCEO) >;4 V in a 0.25-μm InP HBT IC technology for lower end of the THz frequency band.
Abstract: We report on the development of a 0.25-μm InP HBT IC technology for lower end of the THz frequency band (0.3-3 THz). Transistors demonstrate an extrapolated fmax of >;800 GHz while maintaining a common-emitter breakdown voltage (BVCEO) >;4 V. The transistors have been integrated in a full IC process that includes three-levels of interconnects, and backside processing. The technology has been utilized for key circuit building blocks (amplifiers, oscillators, frequency dividers, PLL, etc), all operating at ≥300 GHz. Next, we report a series of fundamental oscillators operating up to 0.57 THz fabricated in a 0.25-μm InP HBT technology. Oscillator designs are based on a differential series-tuned topology followed by a common-base buffer, in a fixed-frequency or varactor-tuned scheme. For ≥400 GHz designs, a subharmonic down-conversion mixer is integrated to facilitate spectrum measurement. At optimum bias, the measured output power was -6.2, -5.6, and -19.2 dBm, for 310.2-, 412.9-, and 573.1-GHz designs, respectively, with PDC ≤ 115 mW. Varactor-tuned designs demonstrated 10.6-12.3 GHz of tuning bandwidth up to 300 GHz.
TL;DR: This paper describes a micropower low-noise neural front-end circuit capable of recording epileptic fast ripples (FR) and is the first to achieve the FR-recording functionality.
Abstract: This paper describes a micropower low-noise neural front-end circuit capable of recording epileptic fast ripples (FR) The front-end circuit consisting of a preamplifier followed by a 6th-order bandpass filter is designed for signal sensing in a future epileptic deep brain stimulator A current-splitting technique is combined with an output-branch current scaling technique in a folded-cascode amplifier structure to improve the noise and power tradeoff in the preamplifier In measurements, the preamplifier exhibits 394 dB DC gain, 036 Hz to 13 kHz of -3 dB bandwidth, and 307 μVrms total input-referred noise while consuming 24 μW from a 28 V power supply provided by an on-chip regulator circuit A noise efficiency factor (NEF) of 309 is achieved with minimal power consumption and is one of the lowest published to date The 6th-order follow-the-leader feedback elliptic bandpass filter passes FR signals and provides -110 dB/decade attenuation to out-of-band frequency components In measurements, the entire front-end circuit achieves a mid-band gain of 385 dB, a bandwidth from 250 to 486 Hz, and a total input-referred noise of 248 μVrms while consuming 45 μW from the 28 V power supply The front-end NEF achieved is 76 To the authors' knowledge, the proposed epileptic seizure- detection system is the first to achieve the FR-recording functionality The chip is fabricated in a standard 06 μm CMOS process Die size is 045 mm2
TL;DR: Variation-aware DVFS with optimal core mapping is shown to improve energy efficiency 6%-35% across a range of compute/communication activity workloads and a new dynamic thread hopping scheme boosts performance by 5%-10% or energy efficiency by 20%-60%.
Abstract: In this paper, we present measured within-die core-to-core Fmax and leakage variation data for an 80-core processor in 65 nm CMOS and 1) populate a parameterized energy/performance model to determine the most energy-efficient operating point for a workload; 2) examine impacts of per-core clock and power gating on optimal dynamic voltage-frequency-core scaling (DVFCS) operating points; and 3) compare improvements in energy efficiency achievable by variation-aware DVFCS and core mapping on Single-Voltage/Multiple-Frequency (SVMF), Multiple-Voltage/Single-Frequency (MVSF) and Multiple-Voltage/Multiple-Frequency (MVMF) designs. Variation-aware DVFS with optimal core mapping is shown to improve energy efficiency 6%-35% across a range of compute/communication activity workloads. A new dynamic thread hopping scheme boosts performance by 5%-10% or energy efficiency by 20%-60%.