An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Two layers of protection films are formed such that a sheet resistance at a portion directly below the protection film is higher than that at a portion directly below the protection film. The protection films are formed, for example, of SiN film, as insulating films. The protection film is formed to be higher, for instance, in hydrogen concentration than the protection film so that the protection film is higher in refractive index the protection film. The protection film is formed to cover a gate electrode and extend to the vicinity of the gate electrode on an electron supplying layer. The protection film is formed on the entire surface to cover the protection film. According to this configuration, the gate leakage is significantly reduced by a relatively simple configuration to realize a highly-reliable compound semiconductor device achieving high voltage operation, high withstand voltage, and high output.

Compound semiconductor device and method of manufacturing the same

Group III-nitride devices are described that include a stack of III-nitride layers, passivation layers, and conductive contacts. The stack includes a channel layer with a 2DEG channel, a barrier layer and a spacer layer. One passivation layer directly contacts a surface of the spacer layer on a side opposite to the channel layer and is an electrical insulator. The stack of III-nitride layers and the first passivation layer form a structure with a reverse side proximate to the first passivation layer and an obverse side proximate to the barrier layer. Another passivation layer is on the obverse side of the structure. Defected nucleation and stress management layers that form a buffer layer during the formation process can be partially or entirely removed.

Reverse side engineered iii-nitride devices

In a nitride semiconductor device according to one embodiment of the invention, a p-type gallium nitride (GaN) layer electrically connected to a source electrode and extending and projecting to a drain electrode side with respect to a gate electrode is formed on an undoped or n-type aluminum gallium nitride (AlGaN) layer serving as a barrier layer

Nitride semiconductor device

A III-N semiconductor device that includes a substrate and a nitride channel layer including a region partly beneath a gate region, and two channel access regions on opposite sides of the part beneath the gate. The channel access regions may be in a different layer from the region beneath the gate. The device includes an AlXN layer adjacent the channel layer wherein X is gallium, indium or their combination, and a preferably n-doped GaN layer adjacent the AlXN layer in the areas adjacent to the channel access regions. The concentration of Al in the AlXN layer, the AlXN layer thickness and the n-doping concentration in the n-doped GaN layer are selected to induce a 2DEG charge in channel access regions without inducing any substantial 2DEG charge beneath the gate, so that the channel is not conductive in the absence of a switching voltage applied to the gate.

Enhancement Mode III-N HEMTs

Integrated high efficiency lateral field effect rectifier and HEMT devices of GaN or analogous semiconductor material, methods for manufacturing thereof, and systems which include such integrated devices. The lateral field effect rectifier has an anode containing a shorted ohmic contact and a Schottky contact, and a cathode containing an ohmic contact, while the HEMT preferably has a gate containing a Schottky contact. Two fluorine ion containing regions are formed directly underneath both Schottky contacts in the rectifier and in the HEMT, pinching off the (electron gas) channels in both structures at the hetero-interface between the epitaxial layers.

Integrated HEMT and Lateral Field-Effect Rectifier Combinations, Methods, and Systems

A method of fabricating AlGaN/GaN enhancement-mode heterostructure field-effect transistors (HFET) using fluorine-based plasma immersion or ion implantation. The method includes: 1) generating gate patterns; 2) exposing the AlGaN/GaN heterostructure in the gate region to fluorine-based plasma treatment with photoresist as the treatment mask in a self-aligned manner; 3) depositing the gate metal to the plasma treated AlGaN/GaN heterostructure surface; 4) lifting off the metal except the gate electrode; and 5) high temperature post-gate annealing of the sample. This method can be used to shift the threshold voltage of a HFET toward a more positive value, and ultimately convert a depletion-mode HFET to an enhancement-mode HFET (E-HFET).

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Enhancement-Mode III-N Devices, Circuits, and Methods

A field-effect transistor includes a first gate, a second gate held at a substantially fixed potential in a cascode configuration, and a semiconductor channel. The semiconductor channel has an enhancement mode portion and a depletion mode portion. The enhancement mode portion is gated to be turned on and off by the first gate, and has been modified to operate in enhancement mode. The depletion mode portion is gated by the second gate, and has been modified to operate in depletion mode and that is operative to shield the first gate from voltage stress.

/pdf/reliable-normally-off-iii-nitride-active-device-structures-1zk75k4vwc.pdf

Reliable normally-off III-nitride active device structures, and related methods and systems

A method for and devices utilizing monolithic integration of enhancement-mode and depletion-mode AlGaN/GaN heterojunction field-effect transistors (HFETs) is disclosed. Source and drain ohmic contacts of HFETs are first defined. Gate electrodes of the depletion-mode HFETs are then defined. Gate electrodes of the enhancement-mode HFETs are then defined using fluoride-based plasma treatment and high temperature post-gate annealing of the sample. Device isolation is achieved by either mesa etching or fluoride-based plasma treatment. This method provides a complete planar process for GaN-based integrated circuits favored in high-density and high-speed applications.

/pdf/monolithic-integration-of-enhancement-and-depletion-mode-2zbdwghwma.pdf

Monolithic Integration of Enhancement- and Depletion-mode AlGaN/GaN HFETs

Methods and devices for fabricating AlGaN/GaN normally-off high electron mobility transistors (HEMTs). A fluorine-based (electronegative ions-based) plasma treatment or low-energy ion implantation is used to modify the drain-side surface field distribution without the use of a field plate electrode. The off-state breakdown voltage can be improved and current collapse can be completely suppressed in LDD-HEMTs with no significant degradation in gains and cutoff frequencies.

Jing Chen

Papers

Integrated HEMT and Lateral Field-Effect Rectifier Combinations, Methods, and Systems

Enhancement-Mode III-N Devices, Circuits, and Methods

Reliable normally-off III-nitride active device structures, and related methods and systems

Monolithic Integration of Enhancement- and Depletion-mode AlGaN/GaN HFETs

Low density drain HEMTs