This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

A transformer-based high-order resonator is proposed to improve the locking range (LR) of the millimeter-wave injection-locked frequency dividers (ILFDs). The LR limitations on ILFDs are discussed, and the operating principles of the proposed high-order resonator are analyzed based on their flattened phase response. The inductive gain peaking technique and the tail current source requirement are further analyzed for low power considerations. Two chips are fabricated in a 65-nm CMOS process to implement the proposed techniques: the first one measures an LR of 62.9% from 27.9 to 53.5 GHz while consuming 5.8 mW from a 1-V power supply and the second chip achieves an LR of 62.7% from 32.4 to 61.9 GHz while consuming only 1.2 mW from a 0.42-V power supply. The best figure of merit can achieve up to 24.7 GHz/mW.

Analysis and Design of Ultra-Wideband mm-Wave Injection-Locked Frequency Dividers Using Transformer-Based High-Order Resonators

This article presents the 38-GHz phased array 32-element Tx and 16-element Rx with 2-GHz IF and 5-GHz LO for fifth-generation (5G) millimeter-wave (MMW) communications. The Tx and Rx beamformers and upconverters/downconverters are fabricated in 65-nm CMOS. The PAs and LNAs near antenna ends are fabricated in 0.15- $\mu \text{m}$ GaAs pHEMT. The eight-element Tx and four-element Rx phased array printed circuit board (PCB) modules integrated with multiple integrated circuits (ICs) and endfire antennas are implemented as unit cells. Four pieces of Tx modules are vertically stacked to construct an $8\times {4}$ brick array (planar array), while four Rx modules are to construct a $4\times {4}$ array. According to 38-GHz over-the-air (OTA) measurements, the 32-element Tx shows 47.5-dBm equivalent isotropic radiated power (EIRP) at OP $_{\mathrm {1 ~dB}}$ with −35.2-dB image rejection ratio (IMRR) and −37.4-dB $\times 8$ LORR. The 16-element Rx at 38 GHz shows −4-dBm OP $_{\mathrm {1~dB}}$ with −28-dB IMRR and −36.6-dB LORR. The Tx and Rx support the beam scanning around ±60° azimuth and ±30° elevation planes. The Tx-to-Rx wireless data link demonstrates 64 quadrature amplitude modulation (QAM)/400 M-BR, 256 QAM/200 M-BR, and 512 QAM/100 M-BR in 20 m. To the best of our knowledge, this work is the first 5G 37-/39-GHz phased array Tx/Rx using the scalable brick array configuration and demonstrating competitive performances compared with previous works.

38-GHz Phased Array Transmitter and Receiver Based on Scalable Phased Array Modules With Endfire Antenna Arrays for 5G MMW Data Links

This paper presents a dual polarized 37-40 GHz transmitter-receiver (TRX) phased array front-end RFIC implemented in a 28nm bulk RF-CMOS process. The TRX front-end contains 8 channels, 4-vertical (V) and 4-horizontal (H). Each transmit (TX) or receive (RX) channel consists of PA or LNA, 5-bit passive phase shifter, coarse and fine gain control amplifiers. The TX channel shows an op1dB of 10.2 dBm at the antenna bump. The RX channel shows a noise figure (NF) of 6 dB. TX and RX channels show an EVM of -32.57 dB and -29.80 dB respectively. A 4×4 antenna array was implemented on PCB using 4 TRX front-end RFICs. Beam patterns with different 5G-modulated waveforms were characterized.

A 37-40 GHz Phased Array Front-end with Dual Polarization for 5G MIMO Beamforming Applications

This article presents a 20–44-GHz image-rejection receiver in GlobalFoundries 22-nm fully-depleted silicon-in-insulator (FD-SOI). The receiver includes a wideband LNA with a three-pole high-pass rejection filter coupled to a double-balanced mixer with a wideband LO driver and an intermediate frequency (IF) amplifier. At an IF of 16 GHz, the image band at dc −12 GHz is filtered by the LNA response and is greater than 75 dB over the entire 20–44-GHz range. The receiver results in a gain of 24–28.5 dB and a noise figure (NF) of 3.3–5 dB at 20–44 GHz and achieves an error vector magnitude (EVM) of 3.6%–3.7% at the carrier frequency of 28 and 39 GHz with 2-Gbaud symbol rate at 64-QAM waveform. To the best of the authors’ knowledge, this is the first wideband image-rejection receiver that covers the entire millimeter-wave 5G band based on GF 22-nm CMOS FD-SOI.

A 20–44-GHz Image-Rejection Receiver With >75-dB Image-Rejection Ratio in 22-nm CMOS FD-SOI for 5G Applications

An injection-current-boosting (ICB) locking-range enhancement technique is presented to increase the locking range (LR) of the millimeter-wave (mm-wave) injection-locked frequency triplers (ILFTs). With a transformer-based fourth-order injection-coupling network, the parallel capacitance from the injection devices is resonated out over a wide frequency range and the injection current is boosted greatly. Analytical models of the ICB–ILFT are introduced, based on which the current-boosting phenomenon is analyzed. Meanwhile, the design concepts of the ultra-wideband mm-wave ILFT are presented. With the proposed ICB technique, an ICB-ILFT is designed and fabricated in 65-nm CMOS process. With a 0-dBm RF injection source, the ICB-ILFT can be locked from 22.8 to 43.2 GHz without calibration, achieving a 61.8% LR. The power consumption is only 5.0 mW and a 9.5-dB phase noise difference is observed, which is close to the theoretical value.

An Injection-Current-Boosting Locking-Range Enhancement Technique for Ultra-Wideband mm-Wave Injection-Locked Frequency Triplers

This paper presents a 39 GHz dual-channel transceiver chipset with LTCC package for 5G fixed wireless access (FWA) communication. The proposed transceiver chipset integrates two variable-gain frequency conversion channels, one LO chain and one SPI block. This chipset is fabricated in a standard 65 nm CMOS process. The TX results a maximum gain of 11 dB and a $\mathbf{P}_{\mathbf{sat}}$ of 8.4 dBm, while the RX supplies a maximum gain of 52 dB, a NF of 5.4 dB and an OP1dB of 7.2 dBm. The single-chan-nel communication link achieves an EVM of 3.72% for 64 QAM modulation and an EVM of 3.76% for 256 QAM modulation over 1 m distance.

A 256-QAM 39 GHz Dual-Channel Transceiver Chipset with LTCC Package for 5G Communication in 65 nm CMOS

Future cross-network and international roaming are attractive in mm-wave fifth-generation (5G) wireless networks with multiband operations. The generation of an ultra-wide-bandwidth ultra-low-phase-noise (PN) local oscillator (LO) signal in massive multiple-input multiple-output (MIMO) transceivers, which support spectra around 28GHz, 37GHz, and 39GHz, becomes a significant challenge. Injection-locked frequency tripler (ILFT) is a good candidate for LO generation due to its low PN property while suffering from a narrow locking range. Varactors are often used to tune the free-running frequency to increase the bandwidth [1]. However, the PN performance degrades when the target frequency is far away from the free-running frequency, which means a complex calibration mechanism must be applied [2,3]. Meanwhile, an ILFT with such a self-calibration circuit still suffers from a narrow locking range, which cannot support multiband operations. To simplify the system design and meet the multiband requirement, a tuning-less ILFT with an ultra-wide locking range is seen as an appropriate solution for mm-wave multiband 5G applications.

A 22.8-to-43.2GHz tuning-less injection-locked frequency tripler using injection-current boosting with 76.4% locking range for multiband 5G applications

An eight-core fundamental VCO with ultralow phase noise (PN) performance is presented. Eight VCOs are in-phase coupled for low PN, and a 9-dB PN improvement is achieved. A scalable layout methodology is presented to solve the layout difficulties in multicore VCOs. Two VCO cores are connected together directly to form a VCO cell. By simply connecting $N$ /2 VCO cells, the PN of the entire multicore VCO will achieve a 10 logN dB PN improvement compared with the single VCO core. The proposed eight-core VCO is fabricated in 65-nm CMOS and occupies 0.15 mm2. The measured PN is −105.5 dBc/Hz at 1-MHz offset, with the tuning range from 62.2 to 67.3 GHz (7.9%). The VCO consumes 61.2-mW power with the figure-of-merit of −183.5 dBc/Hz at 1-MHz offset.

Jingzhi Zhang

Papers

Analysis and Design of Ultra-Wideband mm-Wave Injection-Locked Frequency Dividers Using Transformer-Based High-Order Resonators

An Injection-Current-Boosting Locking-Range Enhancement Technique for Ultra-Wideband mm-Wave Injection-Locked Frequency Triplers

A 256-QAM 39 GHz Dual-Channel Transceiver Chipset with LTCC Package for 5G Communication in 65 nm CMOS

A 22.8-to-43.2GHz tuning-less injection-locked frequency tripler using injection-current boosting with 76.4% locking range for multiband 5G applications

An Ultralow Phase Noise Eight-Core Fundamental 62-to-67-GHz VCO in 65-nm CMOS