In view of the development status of the security of LEO satellite communication system, a comprehensive review, induction, and summary is carried out.

On the Security of LEO Satellite Communication Systems: Vulnerabilities, Countermeasures, and Future Trends

A Viterbi decoder is used in many communication receivers to efficiently decode the received signal that has been convolutional encoded in the transmitter This decoding corrects errors that occur due to noise and other imperfections in the channel and is key to achieve a low bit error rate If the decoder is implemented on a SRAM-based field-programmable gate array (SRAM-FPGA), the radiation-induced soft errors can affect the operation of the Viterbi decoder by corrupting the configuration memory, which can change the circuit functionality and will not be corrected unless the FPGA is reconfigured This makes the protection of Viterbi decoders implemented on SRAM-based FPGAs an important issue In this paper, first, fault injection experiments are conducted to study the effects of soft errors on the configuration memory of an SRAM-FPGA implemented Viterbi decoder Then, an efficient protection technique is proposed and evaluated showing that it can provide an efficient protection with a lower resource usage than the traditional triple modular redundancy approach

Design and Implementation of Configuration Memory SEU-Tolerant Viterbi Decoders in SRAM-Based FPGAs

Turbo codes are widely used in satellite communications. When a turbo decoder is implemented on a field-programmable gate array (FPGA) in a space platform, it will suffer single-event upsets (SEUs) that can cause failures and disrupt communications. Therefore, the protection of turbo decoders implemented on FPGAs is important. In this article, first the reliability of an SRAM-FPGA-implemented turbo decoder to SEUs on user memory and configuration memory is evaluated based on fault injection experiments. Then, based on the features of the turbo decoder and the characteristics of the failures revealed by the reliability study, a duplication with comparison (DWC) scheme is proposed for the protection of the turbo decoder. Experimental results show that the reliability of the protected turbo decoder to SEUs on user memory and configuration memory is improved by 99.4% and 95.6%, respectively. The resource usage is about $2.2\times $ that of an unprotected turbo decoder, which is significantly lower than the more than $3\times $ required by the traditional triple modular redundancy (TMR) protection. Finally, the proposed scheme is compared with another two protection schemes.

Design of SEU-Tolerant Turbo Decoders Implemented on SRAM-FPGAs

This paper presents: (i) A novel method for VHDL implementation of register exchange based soft-hard decision Viterbi decoder in order to augment link margins available for “rover to lander” and “lander to orbiter” telemetry links and its performance evaluation and (ii) Re-encoding based node synchronizer Register exchange method is faster and have low latency as compared to traceback method, but the main disadvantage of register exchange is that it needs large number of registers to store the decoded bits corresponding to each state in trellis Using memory based implementation for path metric computation, survival state management and register exchange, have reduced the large number of registers requirement Bit error rate performance evaluation of the implemented hard and soft decision decoding have been carried out by varying trellis depth and soft quantization bits The performance and threshold evaluation for node synchronizer to decide “In-Sync”, “Out-Of-Sync” have been carried out

A Novel Approach for FPGA Implementation of Register Exchange Based Viterbi Decoder and Re-Encoding based Node Synchronizer

Commercial off-the-shelf (COTS) field-programmable gate arrays (FPGAs) with a 28-nm process have become popular devices for computing systems. Although current generation FPGAs have advantages over previous models, the phenomenon of circuit aging has become more significant with the sharp reduction in the process size of FPGAs. Aging results in FPGA performance degradation over time and, ultimately, hard faults. However, few studies have focused on understanding aging mechanisms or estimating the aging trend of 28-nm FPGAs. For this, we used a ring oscillator (RO)-based test structure to extract data and build a dataset that could be used to predict aging trends and determine the primary aging mechanisms of 28-nm FPGAs. Moreover, we proposed a correction method to correct temperature-induced measurement errors in accelerated tests. Furthermore, we employed four machine learning (ML) technologies that were based on accurate measurement datasets to predict FPGA aging trends. In the experiment, 24 XILINX 7-series FPGAs (28 nm) were evaluated for 10+ years of circuit operation using accelerated tests. The results showed that the aging effects of negative-bias temperature instability (NBTI) was the primary aging mechanism. The correction method proposed in this paper could effectively eliminate measurement errors. In addition, the minimum prediction error rate of the ML model was only 0.292%.

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Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm Process

This paper analyzes the effects of single event upsets (SEUs) on the user memory of a Viterbi decoder implemented on an SRAM based FPGA. First, an FPGA Viterbi decoder implementation is used to study the structures that are mapped to user memory. Then, the SEUs tolerance capability for each of those structures is analyzed theoretically. Finally, fault injection experiments are performed to verify the analysis. Both the analysis and experiment results show that most of SEUs on user memories can be tolerated by the Viterbi decoder, and the lower bit error rate, the better the fault tolerance of the decoder. Even for high bit error rate that exceeds the error correction limit of the decoder, over 95% of SEUs on user memories can be tolerated. The SEUs tolerance analysis and the results will be used to implement a selective hardening of the decoder in the future.

Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi Decoders

Modern satellite communication systems require on-board processing (OBP) for performance improvements, and SRAM-FPGAs are an attractive option for OBP implementation. However, SRAM-FPGAs are sensitive to radiation effects, among which single event upsets (SEUs) are important as they can lead to data corruption and system failure. This paper studies the fault tolerance capability of a SRAM-FPGA implemented Viterbi decoder to SEUs on the user memory. Analysis and fault injection experiments are conducted to verify that over 97% of the SEUs on user memory would not lead to output errors. To achieve a better reliability, selective protection schemes are then proposed to further improve the reliability of the decoder to SEUs on user memory with very small overhead. Although the results are obtained for a specific FPGA implementation, the developed reliability estimation model and the general conclusions still hold for other implementations.

Radiation tolerant viterbi decoders for on-board processing (OBP) in satellite communications

Decimation is widely used in digital communication systems to reduce the oversampling rate of the base band signal. The structure of Poly Phase Filters (PPFs) provides an efficient implementation of the decimator. This paper studies the effects of Single Event Upsets (SEUs) on PPFs based decimators implemented on SRAM-FPGAs. Fault injection experiments are performed to evaluate the reliability of the decimator to SEUs on filter coefficients and on the configuration memory. For the first part, experiment results show that only SEUs on the two most significant bits would cause non negligible SNR loss in the output. For SEUs on the essential bits in the configuration memory, about 20% of them would affect the results, among which 70% of the SEUs would cause negligible SNR loss. The percentage of SEUs that cause a SNR loss larger than 5dB are 7%, 13% and 16% for decimation rates of 16, 8 and 4, respectively. This can be explained as the decimator is composed of a number of parallel filters that is equal to the decimation rate, and each filter contributes a fraction of the final output. Therefore, a SEU on one filter would not cause large degradation to the decimated signal, and the larger the decimation rate is, the smaller the degradation of decimated signal introduced by the SEU.

Reliability Evaluation of Polyphase-filter based Decimators Implemented on SRAM-FPGAs

Estimating the frequency of the elements in a data set is commonly needed in data analysis. With the increase of the size of the data sets, accurately computing the number of times that each element appears with a counter becomes impractical. Instead, the Count Min Sketch (CMS) is widely used in big data processing to estimate frequency due to its simplicity and small storage needs. However, soft errors caused by Single Event Transients (SETs) will affect the hardware implementation of the CMS, mainly the hash functions. In this paper, the effect of SETs on the hash functions of the CMS frequency estimate is analyzed theoretically in terms of overestimation probability, underestimation probability, and the equal probability, and further discussed for data with different frequency. Simulation results verify the correctness of the theoretical analysis and reveal several valuable conclusions. First, a large portion of SETs can be tolerated by the CMS itself, and the reliability of the CMS improves when larger number of arrays are used. Second, the average probability for overestimation and underestimation are almost the same, and decrease for larger numbers of arrays. Third, SETs are more likely to cause underestimation for the most frequent data elements. Finally, the overall effect of SETs on the CMS is slightly affected by the number of counters in each array, and seems to be independent of the distribution of the input sequence. The results and analysis presented in this paper provide a starting point for the design of efficient SET fault-tolerant schemes for the CMS.

Jinhua Zhu

Papers

Design and Implementation of Configuration Memory SEU-Tolerant Viterbi Decoders in SRAM-Based FPGAs

Analysis of the Effects of Single Event Upsets (SEUs) on User Memory in FPGA Implemented Viterbi Decoders

Radiation tolerant viterbi decoders for on-board processing (OBP) in satellite communications

Reliability Evaluation of Polyphase-filter based Decimators Implemented on SRAM-FPGAs

Reliability Evaluation of the Count Min Sketch (CMS) against Single Event Transients (SETs)