Journal of Applied physics,Vol.33 : 1962年に発表されたレオロジー関連の論文

To facilitate the development of future FPGA architectures and CAD tools -- both embedded programmable fabrics and pure-play FPGAs -- there is a need for a large scale, publicly available software suite that can synthesize circuits into easily-described hypothetical FPGA architectures. These circuits should be captured at the HDL level, or higher, and pass through logical and physical synthesis. Such a tool must provide detailed modelling of area, performance and energy to enable architecture exploration. As software flows themselves evolve to permit design capture at ever higher levels of abstraction, this downstream full-implementation flow will always be required. This paper describes the current status and new release of an ongoing effort to create such a flow - the 'Verilog to Routing' (VTR) project, which is a broad collaboration of researchers. There are three core tools: ODIN II for Verilog Elaboration and front-end hard-block synthesis, ABC for logic synthesis, and VPR for physical synthesis and analysis. ODIN II now has a simulation capability to help verify that its output is correct, as well as specialized synthesis at the elaboration step for multipliers and memories. ABC is used to optimize the 'soft' logic of the FPGA. The VPR-based packing, placement and routing is now fully timing-driven (the previous release was not) and includes new capability to target complex logic blocks. In addition we have added a set of four large benchmark circuits to a suite of previously-released Verilog HDL circuits. Finally, we illustrate the use of the new flow by using it to help architect a floating-point unit in an FPGA, and contrast it with a prior, much longer effort that was required to do the same thing.

The VTR project: architecture and CAD for FPGAs from verilog to routing

Pruning and quantization for deep neural network acceleration: A survey

Memristor-based systems and their potential applications, in which memristor is both a nonlinear element and a memory element, have been received significant attention recently. A memristor-based hyperchaotic system with hidden attractor is studied in this paper. The dynamics properties of this hyperchaotic system are discovered through equilibria, Lyapunov exponents, bifurcation diagram, Poincaré map and limit cycles. In addition, its anti-synchronization scheme via adaptive control method is also designed and MATLAB simulations are shown. Finally, an electronic circuit emulating the memristor-based hyperchaotic system has been designed using off-the-shelf components.

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A Memristor-Based Hyperchaotic System with Hidden Attractors: Dynamics, Synchronization and Circuital Emulating

The development of future FPGA fabrics with more sophisticated and complex logic blocks requires a new CAD flow that permits the expression of that complexity and the ability to synthesize to it. In this paper, we present a new logic block description language that can depict complex intra-block interconnect, hierarchy and modes of operation. These features are necessary to support modern and future FPGA complex soft logic blocks, memory and hard blocks. The key part of the CAD flow associated with this complexity is the packer, which takes the logical atomic pieces of the complex blocks and groups them into whole physical entities. We present an area-driven generic packing tool that can pack the logical atoms into any heterogeneous FPGA described in the new language, including many different kinds of soft and hard logic blocks. We gauge its area quality by comparing the results achieved with a lower bound on the number of blocks required, and then illustrate its explorative capability in two ways: on fracturable LUT soft logic architectures, and on hard block memory architectures. The new infrastructure attaches to a flow that begins with a Verilog front-end, permitting the use of benchmarks that are significantly larger than the usual ones, and can target heterogenous FPGAs.

/pdf/architecture-description-and-packing-for-logic-blocks-with-3xt9ct6h4f.pdf

Architecture description and packing for logic blocks with hierarchy, modes and complex interconnect

FPGA is an appealing platform to accelerate DNN. We survey a range of FPGA chip designs for AI. For DSP module, one type of design is to support low-precision operation, such as 9-bit or 4-bit multiplication. The other type of design of DSP is to support floating point multiply-accumulates (MACs), which guarantee high-accuracy of DNN. For ALM (adaptive logic module) module, one type of design is to support low-precision MACs, three modifications of ALM includes extra carry chain, or 4-bit adder, or shadow multipliers which increase the density of on-chip MAC operation. The other enhancement of ALM or CLB (configurable logic block) is to support BNN (binarized neural network) which is ultra-reduced precision version of DNN. For memory modules which can store weights and activations of DNN, three types of memory are proposed which are embedded memory, in-package HBM (high bandwidth memory) and off-chip memory interfaces, such as DDR4/5. Other designs are new architecture and specialized AI engine. Xilinx ACAP in 7 nm is the first industry adaptive compute acceleration platform. Its AI engine can provide up to 8X silicon compute density. Intel AgileX in 10 nm works coherently with Intel own CPU, which increase computation performance, reduced overhead and latency.

A survey of FPGA design for AI era

A radiation hardened resistive SRAM structure (rSRAM) is proposed for the SRAM-based FPGAs in this paper. The rSRAM extends the conventional 6T SRAM structure by connecting memristors between the information nodes and drains of the transistors which compose cross-coupled invertors. With memristors connected to drains of OFF transistors configured to high resistance state while others configured to low resistance state forming stable voltage dividing path, the rSRAM structure is immune to both multiple-node upsets and multiplebit upsets (MBUs). The simulation result demonstrates that rSRAM cell can tolerate simultaneous disruptions affecting all sensitive nodes with an LET (Liner Energy Transfer) of 100Mev-cm2/mg.

/pdf/a-novel-memristor-based-rsram-structure-for-multiple-bit-34e2c2pqat.pdf

A novel memristor-based rSRAM structure for multiple-bit upsets immunity

A platform-independent multithread routing method for FPGAs is proposed in this paper. Specifically, the proposed method includes two aspects for maximal parallelization. First, for high fanout net which usually takes considerable time to be routed due to large bounding boxes and number of terminals, it is partitioned into several subnets to be routed in parallel. Second, low fanout nets with non-overlapping bounding boxes are identified and routed in parallel as well to further speed up the routing process. A bounding box graph was constructed to facilitate the process of selecting nets to be routed concurrently. In addition, load balancing and synchronization strategies are introduced to raise routing efficiency and ensure the deterministic results. Experiments on different platforms and benchmarks with various combinations of high and low fanout nets are carried out. This technique improves the run-time by ~1.9 × with routing quality degrading by no more than 2.3%, on a quad-core processor platform.

A novel net-partition-based multithread FPGA routing method

In this paper, we present a new placement algorithm targeted on a modern FPGA with heterogeneous logic and routing resources. This algorithm divides the heterogeneous resources of an FPGA into different logic layers, obtains a good initial placement by a quadratic method, and then employs low-temperature simulated annealing on each logic layer to determine the final location for all modules. Experiment result shows that the algorithm not only gains a saving of runtime by 27% compared with the classical approach of Versatile Place and Route (VPR) while having the same performance, but is also highly adaptable to modern FPGAs which have heterogeneous logic and routing resources1.

A New FPGA placement algorithm for heterogeneous resources

Logic block packing is a necessary procedure of synthesis in FPGA CAD flow. In academic field, the existent packing algorithm, such as TV-Pack, is architecture-dependent and only applied to a certain type of logic blocks. In this paper, a novel function level modeling method for logic block is proposed. Furthermore, universal pack, a universal logic block packing algorithm based on this modeling, is presented and implemented. The experimental results show that this algorithm is architecture-independent and able to deal well with different types of logic blocks. Then the modeling method is proved to be right and quite effective for logic block packing

Jinmei Lai

Papers

A survey of FPGA design for AI era

A novel memristor-based rSRAM structure for multiple-bit upsets immunity

A novel net-partition-based multithread FPGA routing method

A New FPGA placement algorithm for heterogeneous resources

A new FPGA packing algorithm based on the modeling method for logic block