The remarkable growth of wireless data traffic in recent times has driven the need to explore suitable regions in the radio spectrum to meet the projected requirements. In pursuance of this, millimeter wave communications have received considerable attention in the research fraternity. Due to the high path and penetration losses at millimeter wavelengths, antenna beamforming assumes a pivotal role in establishing and maintaining a robust communication link. Beamforming for millimeter wave communications poses a multitude of diverse challenges due to the large channel bandwidth, unique channel characteristics, and hardware constraints. In this paper, we track the evolution and advancements in antenna beamforming for millimeter wave communications in the context of the distinct requirements for indoor and outdoor communication scenarios. We expand the scope of discussion by including the developments in radio frequency system design and implementation for millimeter wave beamforming. We explore the suitability of millimeter wave beamforming methods, both, existing and proposed till midyear 2015, and identify the exciting new prospects unfolding in this domain.

Beamforming for Millimeter Wave Communications: An Inclusive Survey

A fully integrated 60-GHz 5-Gb/s quadrature phase-shift keying (QPSK) transceiver with the transmit/receive (T/R) switch in 65-nm CMOS is presented. By utilizing the co-design of the T/R switch with the power amplifier (PA)/low-noise amplifier, π-type wideband passive network technique, as well as the modified distributed-amplifier-based PA, the RF bandwidth of the transmitter (TX)/receiver (RX) is extended to 5 GHz. An inductorless wideband programmable gain amplifier with negative capacitive neutralization, consisting of two modified Cherry-Hooper amplifier stages, provides 18-dB variable gain range with enough bandwidth. Due to the proposed bandwidth extension techniques, the measured double-side link bandwidth of the TX/RX is wider than 5 GHz so that 5-Gb/s QPSK communication could be supported. A direct QPSK modulator and mixed-signal QPSK demodulator are integrated to avoid the high-power high-complexity analog-digital converter/digital-analog converter and high-speed digital baseband processing. Together with the integrated T/R switch, the power consumption and the cost of the transceiver are significantly lowered while achieving up to 5-Gb/s data rate. The local oscillating signals and various clocks are provided by a fully differential phase-locked loop frequency synthesizer with -97.2-dBc/Hz phase noise at 1-MHz offset from a 40-GHz carrier. The measured error vector magnitude of the TX is -21.9 dB, while the bit error rate of the RX with a -52-dBm sine-wave input is below 8e-7 when transmitting/receiving 5-Gb/s data. The transceiver is powered by 1.0- and 1.2-V supply (except the phase-frequency detector and charge-pump in the frequency synthesizer, which are powered by a 2.5-V supply) and consumes 135 mW in the TX mode and 176 mW in the RX mode, with a chip area of 3 mm × 2 mm.

A Fully Integrated 60-GHz 5-Gb/s QPSK Transceiver With T/R Switch in 65-nm CMOS

This paper presents the design and verification of a proposed 30-GHz power-efficient phase-locked loop (PLL) frequency synthesizer for 60-GHz applications Fabricated by a commercial 018- $\mu \text{m}$ SiGe BiCMOS process, the synthesizer employs coupled LC tank voltage-controlled oscillator, high power-added efficiency amplifier, reconfigurable divider realizing fractional division ratios for choice of multiple reference frequencies and low operation power, a programmable charge pump, an internal loop filter, and an integrated slave serial peripheral interface The PLL synthesizer (PLLS) provides output frequency from 295 to 334 GHz with phase noise of −97 dBc/Hz at 1-MHz offset The integrated phase noise over the frequency of 10 kHz–10 MHz is 205° rms at a frequency of 3024 GHz Operating with a single 18-V supply voltage, the PLLS consumes a low power of 63 mW and occupies an area of 28 mm $\times$ 186 mm

A 30-GHz Power-Efficient PLL Frequency Synthesizer for 60-GHz Applications

This paper discusses some challenges in the design of millimeter-wave (mmwave) circuits and systems for 5th generation (5G) wireless systems in CMOS process. The properties of some passive and active devices such as inductors, capacitors, transmission lines, transformers and transistors in mm-wave frequency band are discussed. Self-healing technique dealing with PVT variation, resonant mode switching technique to enhance frequency tuning range of voltage controlled oscillator (VCO) and dual mode technique for power amplifier (PA) efficiency enhancement are introduced. At last, A fully-integrated 60 GHz 5 Gb/s QPSK transceiver with the transmit/receive (T/R) switch in 65nm CMOS process is introduced. The measured error vector magnitude (EVM) of the TX is -21.9 dB while the bit error rate (BER) of the RX with a -52 dBm sine-wave input is below 8e-7 when transmitting/receiving 5 Gb/s data. The transceiver is powered by 1.0 V and 1.2 V supply (except the phase-frequency detector and charge-pump in the frequency synthesizer which are powered by 2.5 V supply) and consumes 135 mW in TX mode and 176 mW in RX mode.

Research on CMOS mm-wave circuits and systems for wireless communications

The paper presents a comprehensive closed-form performance analysis framework for multihop communications over Weibull fading channels. The analyzed scheme consists basically of multiple regenerative relays with generalized high-order quadrature amplitude modulation (M-QAM) transmissions. To take into consideration the channel fading in the mmWave range, we adopt the advocated Weibull model for its flexible ability to cover different channel conditions. The end-to-end performance is evaluated in terms of outage probability, bit error probability (BER), symbol error probability (SER), block error rate (BLER), ergodic capacity, and energy efficiency (EE). For all the metrics, we present exact closed-form expressions along with their asymptotic behavior, some in terms of generalized hypergeometric functions. Based on the obtained analytical results, we also present a practical application, we derive two BER- and EE-optimal transmit power allocation strategies, and we discuss the resulting performance gains. The exactness of our analysis is illustrated by numerical examples, and assessed via Monte-Carlo simulations for different system and channel parameters. Finally, as a secondary contribution, noting the increasing popularity of Fox's H and bivariate H functions, we provide new and generalized codes for computing these functions which are of practical utility in different contexts.

On Multihop Weibull-Fading Communications: Performance Analysis Framework and Applications

This paper presents our developed two-chip wireless communication system adhering to the IEEE 802.11ad standards with a baseband IC (BBIC) integrated with a low power 60 GHz transceiver SOC (RFIC) and antennas. The novel low power 60GHz RFIC using a sub-harmonic sliding-IF scheme is fully integrated based on low cost SiGe 0.18 um BiCMOS process. The BBIC uses an adaptive time domain equalizer rather than the commonly used frequency domain equalizer to lower the requirements on power consumption.

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An integrated 60GHz low power two-chip wireless system based on IEEE802.11ad standard

A new sub-harmonic QPSK architecture is proposed for microwave and millimeter-wave applications including transceiver. The developed 60GHz differential quadrature sub-harmonic QPSK modulator based on the proposed new QPSK architecture can not only reject both the image frequency and LO leakages but also reduce the LO operation frequency to the half of the conventional modulator. Moreover, the proposed QPSK modulator provide flexibility to select either the low sideband (LSB) or upper side band (USB) and support data rate as high as 3.52Gbps. The compact chip size is only 400um×300um and power consumption of 28mW is much smaller as compared to that of the state of the arts.

A miniaturized 28mW 60GHz differential quadrature sub-harmonic QPSK modulator in 0.18um SiGe BiCMOS

This paper presents a new multi-conversion super heterodyne architecture for 60GHz broadband wireless application. The proposed design consists of a three-stage conversion with the help of a 24GHz VCO and a divider. The local oscillator frequency stands far away from RF and both IF signals reduce inter-modulate interference. The first and second mixers sharing the same 24GHz VCO relax the complexity and lowering power consumption of both VCO and PLL. Reusing of LO signal without frequency doublers or triplers for multiple conversions reduces power, area and improves efficiency. The topology is symmetrical about the transmitter and receiver sections. This unique feature reduces any circuit mismatches and provides a balance load for the VCO. The proposed design is simulated with ADS at the system level. The transceiver shows high sensitivity and indicates low power design on chip.

A fully symmetrical 60GHz transceiver architecture for IEEE 802.15.3c application

This article presents a novel Ka-band Marchand balun implemented in 0.13-μm SiGe bipolar complementary metal–oxide–semiconductor (BiCMOS) process. By combining both edge- and broadside-coupled structures, the new hybrid balun is able to increase the coupling and minimize the balun insertion loss. As compared with conventional edge-coupled or broadside-coupled structures, the proposed balun achieves the lowest insertion loss of 1.02 dB across a wide 1-dB bandwidth from 29.0 GHz to 46.0 GHz, with a core size of 270 μm × 280 μm.

https://www.mdpi.com/2079-9292/9/7/1116/pdf

Ka-Band Marchand Balun with Edge- and Broadside-Coupled Hybrid Configuration

This paper proposes a wide-band self-demodulating receiver for 60GHz ISM band applications. The proposed receiver architecture self-demodulates the OOK input signal by using injection locked oscillator and passive mixer. This simple architecture features extremely ultra-lower-power consumption and faster settling time. Implemented in Tower Jazz 180nm SiGe technology with 200GHz f T , the proposed receiver is able to work at the 60GHz ISM-band frequency range with an OOK data rate up to 2Gbps. The current consumption of the whole receiver is less than 15mA from a single 1.8V supply.

Jinna Yan

Papers

An integrated 60GHz low power two-chip wireless system based on IEEE802.11ad standard

A miniaturized 28mW 60GHz differential quadrature sub-harmonic QPSK modulator in 0.18um SiGe BiCMOS

A fully symmetrical 60GHz transceiver architecture for IEEE 802.15.3c application

Ka-Band Marchand Balun with Edge- and Broadside-Coupled Hybrid Configuration

A 60GHz BiCMOS self-demodulator with injection locked oscillator