The remarkable growth of wireless data traffic in recent times has driven the need to explore suitable regions in the radio spectrum to meet the projected requirements. In pursuance of this, millimeter wave communications have received considerable attention in the research fraternity. Due to the high path and penetration losses at millimeter wavelengths, antenna beamforming assumes a pivotal role in establishing and maintaining a robust communication link. Beamforming for millimeter wave communications poses a multitude of diverse challenges due to the large channel bandwidth, unique channel characteristics, and hardware constraints. In this paper, we track the evolution and advancements in antenna beamforming for millimeter wave communications in the context of the distinct requirements for indoor and outdoor communication scenarios. We expand the scope of discussion by including the developments in radio frequency system design and implementation for millimeter wave beamforming. We explore the suitability of millimeter wave beamforming methods, both, existing and proposed till midyear 2015, and identify the exciting new prospects unfolding in this domain.

Beamforming for Millimeter Wave Communications: An Inclusive Survey

A wideband low-noise amplifier (LNA) based on the current-reused cascade configuration is proposed. The wideband input-impedance matching was achieved by taking advantage of the resistive shunt-shunt feedback in conjunction with a parallel LC load to make the input network equivalent to two parallel RLC-branches, i.e., a second-order wideband bandpass filter. Besides, both the inductive series- and shunt-peaking techniques are used for bandwidth extension. Theoretical analysis shows that both the frequency response of input matching and noise figure (NF) can be described by second-order functions with quality factors as parameters. The CMOS ultra-wideband LNA dissipates 10.34-mW power and achieves S 11 below -8.6 dB, S 22 below -10 dB, S 12 below -26 dB, flat S 21 of 12.26 ± 0.63 dB, and flat NF of 4.24 ± 0.5 dB over the 3.1-10.6-GHz band of interest. Besides, good phase linearity property (group-delay variation is only ±22 ps across the whole band) is also achieved. The analytical, simulated, and measured results agree well with one another.

Analysis and Design of a CMOS UWB LNA With Dual- $RLC$ -Branch Wideband Input Matching Network

This paper presents a wideband low-noise amplifier (LNA) based on the cascode configuration with resistive feedback. Wideband input-impedance matching was achieved using a shunt-shunt feedback resistor in conjunction with a preceding π -match network, while the wideband gain response was obtained using a post-cascode inductor (LP), which was inserted between the output of the cascoding transistor and the input of the shunt-shunt resistive feedback network to enhance the gain and suppress noise. Theoretical analysis shows that the frequency response of the power gain, as well as the noise figure (NF), can be described by second-order functions with quality factors or damping ratios as parameters. Implemented in 90-nm CMOS technology, the die area of this wideband LNA is only 0.139 mm2 including testing pads. It dissipates 21.6-mW power and achieves S11 below -10 dB, S22 below -10 dB, flat S21 of 9.6 ±1.1 dB, and flat NF of 3.68 ± 0.72 dB over the 1.6-28-GHz band. Besides, excellent input third-order inter-modulation point of +4 dBm is also achieved. The analytical, simulated, and measured results are mutually consistent.

Analysis and Design of a 1.6–28-GHz Compact Wideband LNA in 90-nm CMOS Using a $ \pi $ -Match Input Network

In this paper, a low-power full-band low-noise amplifier (FB-LNA) for ultra-wideband applications is presented. The proposed FB-LNA uses a stagger-tuning technique to extend the full bandwidth from 3.1 to 10.6 GHz. A current-reused architecture is employed to decrease the power consumption. By using an input common-gate stage, the input resistance of 50 Ω can be obtained without an extra input-matching network. The output matching is achieved by cascading an output common-drain stage. FB-LNA was implemented with a TSMC 0.18-μm CMOS process. On-wafer measurement shows an average power gain of 9.7 dB within the full operation band. The input reflection coefficient and the output reflection coefficient are both less than -10 dB over the entire band. The noise figure of the full band remained under 7 dB with a minimum value of 5.27 dB. The linearity of input third-order intercept point is -2.23 dBm. The power consumptions at 1.5-V supply voltage without an output buffer is 4.5 mW. The chip area occupies 1.17 × 0.88 mm2.

A Low-Power Full-Band Low-Noise Amplifier for Ultra-Wideband Receivers

The IEEE 802.15.4 standard relaxes the requirements on the receiver front-end making subthreshold operation a viable solution. The specification is discussed and guidelines are presented for a small area ultra-low-power design. A subthreshold biased low-noise amplifier (LNA) has been designed and fabricated for the 2.4-GHz IEEE 802.15.4 standard using a standard low-cost 0.18-mum RF CMOS process. The single-stage LNA saves on chip area by using only one inductor. The measured gain is more than 20 dB with an S11 of -19 dB while using 630 muA of dc current. The measured noise figure is 5.2 dB.

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A Subthreshold Low-Noise Amplifier Optimized for Ultra-Low-Power Applications in the ISM Band

An ultra-wideband (UWB) 3.1- to 10.6-GHz low-noise amplifier (LNA) employing a common-gate stage for wideband input matching is presented in this paper. Designed in a commercial 0.18-mum 1.8-V standard RFCMOS technology, the proposed UWB LNA achieves fully on-chip circuit implementation, contributing to the realization of a single-chip CMOS UWB receiver. The proposed UWB LNA achieves 16.7plusmn0.8 dB power gain with a good input match (S11<-9 dB) over the 7500-MHz bandwidth (from 3.1 GHz to 10.6 GHz), and an average noise figure of 4.0 dB, while drawing 18.4-mA dc biasing current from the 1.8-V power supply. A gain control mechanism is also introduced for the first time in the proposed design by varying the biasing current of the gain stage without influencing the other figures of merit of the circuit so as to accommodate the UWB LNA in various UWB wireless transmission systems with different link budgets

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A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers

This paper presents our developed two-chip wireless communication system adhering to the IEEE 802.11ad standards with a baseband IC (BBIC) integrated with a low power 60 GHz transceiver SOC (RFIC) and antennas. The novel low power 60GHz RFIC using a sub-harmonic sliding-IF scheme is fully integrated based on low cost SiGe 0.18 um BiCMOS process. The BBIC uses an adaptive time domain equalizer rather than the commonly used frequency domain equalizer to lower the requirements on power consumption.

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An integrated 60GHz low power two-chip wireless system based on IEEE802.11ad standard

Designs and techniques for improving the linearity of the power amplifiers, especially of the non-linear types, operated in microwave and millimeter-wave frequency using method through purposely designed active transistors or passive devices or both, are disclosed. The techniques use the manipulation of transistors' cut-off frequencies (fT) design, attached loaded linearization stub and characteristics of space attenuation of microwave signals individually or in combination of them. The disclosed techniques provide the advantages to compromise the performance among linearity, gain and power consumption in a wide range of power amplifier types, such as Class- AB, B, C, D, E and F in the different application scenarios.

Power amplifier and linearization techniques using active and passive devices

A miniature passive structure for electrostatic discharge (ESD) protection and input/output (I/O) matching for a high frequency integrated circuit is provided. The miniature passive structure includes at least one shunt stub and at least one load line. The shunt stub(s) each provide a corresponding ESD discharge path. The load line(s) are coupled to the shunt stub(s) and provide loading effects for the shunt stub(s).

Miniature passive structures for ESD protection and input and output matching

A 60GHz Wilkinson power divider using the meander lines with the floating defect grounding structure (DGS) is introduced and implemented by using the 0.18μm SiGe BiCMOS technology. The slow-wave characteristics of the meander-line and the floating defected ground structure are investigated and used for miniaturized power divider implementation. The dividers using poly resistor and metal resistor are also compared experimentally. The measured results show the frequency covers 40GHz∼70GHz with the insertion loss of 2dB and isolation of better than 15dB. The phase balance is better than 2degrees and the amplitude balance is better than 0.1dB. The size of the divider is only 300μm by 300μm, which can be economically integrated with 60GHz radio chipset.

Yang Lu

Papers

A novel CMOS low-noise amplifier design for 3.1- to 10.6-GHz ultra-wide-band wireless receivers

An integrated 60GHz low power two-chip wireless system based on IEEE802.11ad standard

Power amplifier and linearization techniques using active and passive devices

Miniature passive structures for ESD protection and input and output matching

A 60GHz defected ground power divider using SiGe BiCMOS technology