A geometric program (GP) is a type of mathematical optimization problem characterized by objective and constraint functions that have a special form. Recently developed solution methods can solve even large-scale GPs extremely efficiently and reliably; at the same time a number of practical problems, particularly in circuit design, have been found to be equivalent to (or well approximated by) GPs. Putting these two together, we get effective solutions for the practical problems. The basic approach in GP modeling is to attempt to express a practical problem, such as an engineering analysis or design problem, in GP format. In the best case, this formulation is exact; when this is not possible, we settle for an approximate formulation. This tutorial paper collects together in one place the basic background material needed to do GP modeling. We start with the basic definitions and facts, and some methods used to transform problems into GP format. We show how to recognize functions and problems compatible with GP, and how to approximate functions or data in a form compatible with GP (when this is possible). We give some simple and representative examples, and also describe some common extensions of GP, along with methods for solving (or approximately solving) them.

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A tutorial on geometric programming

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Design Of Analog Cmos Integrated Circuits

We consider the problem of fitting a convex piecewise-linear function, with some specified form, to given multi-dimensional data. Except for a few special cases, this problem is hard to solve exactly, so we focus on heuristic methods that find locally optimal fits. The method we describe, which is a variation on the K-means algorithm for clustering, seems to work well in practice, at least on data that can be fit well by a convex function. We focus on the simplest function form, a maximum of a fixed number of affine functions, and then show how the methods extend to a more general form.

/pdf/convex-piecewise-linear-fitting-49d8ptyg8q.pdf

Convex piecewise-linear fitting

A source-series-terminated (SST) transmitter in a 65 nm bulk CMOS technology is presented. The circuit exhibits an eye height greater than 1.0 V for data rates of up to 8.5 Gb/s. A thin-oxide pre-driver stage running at 1.0 V drives 22 parallel connected thick-oxide SST output stages operated at 1.5 V that feature a 5-bit 2-tap FIR filter whose adaptation is independent of the impedance tuning. To achieve a return loss of <-16 dB up to 10 GHz a 40 mum times 40 mum T-coil complements the transmitter output. This half-bit-rate clock SST transmitter has a duty-cycle restoration capability of 5x, and the common-mode voltage noise is below 10 mV rms for high-, mid- and low-level terminations. The chip consumes 96 mW at 8.5 Gb/s and occupies 180 mum times 360 mum. In addition to the transmitter design, guidelines for the T-coil design are presented.

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A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With $≪ -$ 16 dB Return Loss Over 10 GHz Bandwidth

We propose a new, nonparametric method for multivariate regression subject to convexity or concavity constraints on the response function. Convexity constraints are common in economics, statistics, operations research, financial engineering and optimization, but there is currently no multivariate method that is stable and computationally feasible for more than a few thousand observations. We introduce convex adaptive partitioning (CAP), which creates a globally convex regression model from locally linear estimates fit on adaptively selected covariate partitions. CAP is a computationally efficient, consistent method for convex regression. We demonstrate empirical performance by comparing the performance of CAP to other shape-constrained and unconstrained regression methods for predicting weekly wages and value function approximation for pricing American basket options.

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Multivariate convex regression with adaptive partitioning

We present techniques for improving the accuracy of geometric-programming (GP) based analog circuit design optimization. We describe major sources of discrepancies between the results from optimization and simulation, and propose several methods to reduce the error. Device modeling based on convex piecewise-linear (PWL) function fitting is introduced to create accurate active and passive device models. We also show that in selected cases GP can enable nonconvex constraints such as bias constraints using monotonicity, which help reduce the error. Lastly, we suggest a simple method to take the modeling error into account in GP optimization, which results in a robust design over the inherent errors in GP device models. Two-stage operational amplifier and on-chip spiral inductor designs are given as examples to demonstrate the presented ideas.

Techniques for improving the accuracy of geometric-programming based analog circuit design optimization

This paper presents a foreground calibration method for both a sampler and a track-and-hold (T/H) buffer bandwidth mismatch in highly time-interleaved analog-to-digital converters (TI-ADCs). The T/H buffer bandwidth mismatch stems from the length difference of interconnect lines between the buffer and the channel ADC, while the sampler bandwidth mismatch arises from the mismatch in a switch and a sampling capacitor. To address both mismatches along with other mismatches residing in TI-ADCs, this papers utilizes least-squares (LS) minimization technique in order to extract mismatch parameters while injecting a sinewave at two distinct frequencies. Programmable capacitor arrays (PCAs) are used to tune the bandwidth of sampler, and correcting buffer bandwidth mismatch is performed in digital-domain. The method presented here is scalable to arbitrary number of interleaved paths, and can easily be combined with existing calibration methods for gain, offset, and timing-skew mismatches. Numerical experiment via Monte-Carlo simulations demonstrates significant performance improvement in the spurious-free dynamic range (SFDR) from 38 dB to 75 dB for a 32-channel time-interleaved ADC model that includes all major mismatches.

A Scalable Bandwidth Mismatch Calibration Technique for Time-Interleaved ADCs

A 0.8-V resistor-based CMOS temperature sensor in 65-nm CMOS process with low supply sensitivity is presented. The temperature-to-voltage conversion gain is maximized by utilizing two types of on-chip resistors with positive and negative temperature coefficient. Reusing the resistor sensor frontend as a reference, the voltage generator of the subsequent A/D converter inherently removes the supply dependence of temperature-to-digital conversion. A 10-bit sub-ranging A/D converter employing 5-bit amplifying interpolation D/A converter enables low-voltage and low-noise A/D conversion. Over a range of −45 °C ~ 85 °C, the proposed sensor achieves 0.12 ° ${\mathrm {C}}_{\mathrm{ rms}}$ temperature resolution with a conversion time of $10~ \mu \text{s}$ . After a 2-point calibration, the sensor achieves an inaccuracy of less than +1.6/−1 °C while consuming 47 $\mu \text{W}$ from 0.8-V supply voltage. Measured supply sensitivity is 0.28 °C/V over 0.6 ~1.2 V, which is one of the lowest ever reported among sub-1-V temperature-to-digital converter designs.

A 0.8-V Resistor-Based Temperature Sensor in 65-nm CMOS With Supply Sensitivity of 0.28 °C/V

This paper presents a new method for fitting a convex piecewise-linear function to a given set of data, which can serve as an empirical modeling framework for circuit optimization via geometric programming. The method iteratively solves a series of linear optimization problems to minimize the fitting error. To reduce the fitting error in each iteration, an extra plane is added in the region where the largest error occurs. For verification, we apply the method to create transistor-level models in 90-nm complementary metal-oxide-semiconductor technology. Numerical results indicate that the proposed method can generate process-dependent transistor-level models with reasonable modeling accuracy.

Convex Piecewise-Linear Modeling Method for Circuit Optimization via Geometric Programming

Power dissipation of analog and mixed-signal circuits has emerged as a critical design constraint in today's VLSI systems. This paper presents a multilevel design optimization approach for reducing the power dissipation of a pipelined analog-to-digital converter (ADC). At the circuit-level, device-types and supply-voltages are jointly optimized for the residue amplifier of a pipeline stage to minimize power. At the architecture-level, the nonlinearity contribution from stage gain error is optimally distributed to further minimize combined power dissipation. The optimizations take advantage of an analytical optimization method based on geometric programming for a quantitative tradeoff analysis. All of the proposed power optimizations are applied to the design of a two-way interleaved 8-bit 320 MS/s pipelined ADC in 90-nm CMOS technology. Measured performance from a prototype chip shows 7.30-bit of ENOB at Nyquist input frequency with DNL of -0.35/+0.45 LSB and INL of -0.72/+0.89 LSB, while dissipating 12.77 mW from 2.1 V/1.2 V supplies. The achieved conversion efficiency is 253fJ/conv-step.

Jintae Kim

Papers

Techniques for improving the accuracy of geometric-programming based analog circuit design optimization

A Scalable Bandwidth Mismatch Calibration Technique for Time-Interleaved ADCs

A 0.8-V Resistor-Based Temperature Sensor in 65-nm CMOS With Supply Sensitivity of 0.28 °C/V

Convex Piecewise-Linear Modeling Method for Circuit Optimization via Geometric Programming

Multilevel Power Optimization of Pipelined A/D Converters