A system is described for displaying images of a virtual three-dimensional book having one or more virtual pages. The system comprises a display system capable of executing a display program wherein images of the virtual three-dimensional book are produced on the display system. A degree of interest (DOI) function is provided for allocating available space on the display system. A page selection function may provide a user-selectable scale along a long axis of the virtual book for selecting virtual pages. Virtual chapter tabs may also be provided for navigating within the virtual book. The display system may also include a page flipping function with several different page flipping speeds and several different page flipping animations for moving between virtual pages in the virtual book. Moreover, a scroll bar function provided to facilitate page navigation wherein space on the scroll bar is allocated using a DOI function. Finally, a computer program product comprising a computer usable medium having computer readable code embodied therein for producing images of a virtual three-dimensional book is also disclosed.

Navigation methods, systems, and computer program products for virtual three-dimensional books

Operation in the subthreshold region most often is synonymous to minimum-energy operation. Yet, the penalty in performance is huge. In this paper, we explore how design in the moderate inversion region helps to recover some of that lost performance, while staying quite close to the minimum-energy point. An energy-delay modeling framework that extends over the weak, moderate, and strong inversion regions is developed. The impact of activity and design parameters such as supply voltage and transistor sizing on the energy and performance in this operational region is derived. The quantitative benefits of operating in near-threshold region are established using some simple examples. The paper shows that a 20% increase in energy from the minimum-energy point gives back ten times in performance. Based on these observations, a pass-transistor based logic family that excels in this operational region is introduced. The logic family operates most of its logic in the above-threshold mode (using low-threshold transistors), yet containing leakage to only those in subthreshold. Operation below minimum-energy point of CMOS is demonstrated. In leakage-dominated ultralow-power designs, time-multiplexing will be shown to yield not only area, but also energy reduction due to lower leakage. Finally, the paper demonstrates the use of ultralow-power design techniques in chip synthesis.

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Ultralow-Power Design in Near-Threshold Region

An electronic programming guide ('EPG') provides pictograms (120, 121, 122) and logos (110, 111, 112) to indicate what television programs are showing. The EPG information can be displayed in a window within a television screen (102) while a program is shown on the remainder of the screen (102). Thus, the viewer can know what is playing on the various channels while watching one of the channels. The EPG comprises surfaces located in virtual 3D space and a 3D graphics pipeline applies the pictograms, logos, alphanumeric text and/or video clips to the geometric surfaces. The pictograms, logos, alphanumeric data and/or video clip appereance can be modified using a remote controller (150), e.g. by changing the geometric surface position or lighting. Optionally, internet HTML pages are parsed and applied to geometric surfaces in 3D virtual space.

Electronic Programming Guide

There is disclosed a method, an apparatus, a server, a client and a non-transitory computer readable medium comprising a computer program stored therein for motion compensated video coding and decoding. Texture block motion information is used to derive disparity/depth motion information. Alternatively, disparity/depth motion information is used to derive texture block motion information.

An apparatus, a method and a computer program for video coding and decoding

For large, complex ICs, engineers need efficient techniques for debugging first silicon. The system presented here consists of an on-chip debug infrastructure and supporting debugger software,which interacts with the infrastructure to make the chip's features accessible through a serial interface.

Design for debug: catching design errors in digital chips

A filter structure is provided that facilitates the use of the filter as either a continuous delay Farrow filter or a selectable delay polyphase filter. The less complex polyphase filter is used when the desired scale substantially corresponds to a defined phase of the polyphase filter, or when time or power is not available to achieve the desired scale exactly; otherwise, the continuous delay Farrow filter is used. By providing an ability to switch to a continuous delay, the number of stages of the polyphase filter can be reduced. Additionally, an inversion of a Farrow filter is presented that provides for a continuous delay decimation filter with substantially reduced computational complexity compared to a direct embodiment of a Farrow filter. This inverted filter is also configurable as a polyphase filter, to provide selectable scale-resolution capabilities.

Image interpolation and decimation using a continuously variable delay filter and combined with a polyphase filter

The two dimensional sample rate conversion capabilities of a video display system are used to produce three-dimensional effects. Linear and non-linear scaling is applied to a video image to convey a sense of depth. The three dimensional effects are used to increase the visual appeal of existing and new feature sets in display systems. A multi-faceted object representation, such as a representation of a cube or a pyramid, can be used to display different video images on each facet of the representation. By appropriately scaling each image on each facet, an impression of depth is achieved. The images on the different facets can be selected to represent different aspects of a common theme, such as datacast information related to a primary source of information. Channel changing on a television can be presented as a rotation of the multifaceted object. In like manner, other familiar representations, such as a representation of a book can be used, wherein channel changing is presented as a turning of the pages of the book, each television program being presented on a different page. Advanced features, such as program categorization, can be represented as tabs on the book that facilitate the selection of a particular category. In like manner, a rotation of a multifaceted object about one axis may correspond to a change of channel within a select category, whereas a rotation about another axis may correspond to a change of category. Techniques are presented for achieving these three dimensional effects with calculations that are well suited for execution via the sample rate converters of conventional display systems.

Video sample rate conversion to achieve 3-D effects

This paper presents an application domain driven approach to the design of embedded systems on silicon, and it shows how this approach is used to design a chip for a multi-window TV application. We discuss all major design steps in a logical order starting with an application domain analysis. This leads to the choice of Kahn data flow graphs as the programming paradigm for high-throughput signal applications. Based on this analysis we designed a multiprocessor architecture which uses a run-time reconfiguration. Finally, attention is directed towards the physical implementation and the deep-submicron problems we had to solve. The result is a chip that can manage up to 25 internal real-time video streams. The chip combines the flexibility of a programmable solution with the cost effectiveness of a consumer product.

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Heterogeneous multi-processor for the management of real-time video and graphics streams

There is disclosed an apparatus for sharpening an edge in a video image. The apparatus comprises: 1) a first circuit for determining a first luminance value of a first pixel associated with the first edge and a second luminance value of a second pixel associated with the first edge, wherein the first and second pixels are adjacent pixels; 2) a second circuit for determining a position of a first subpixel disposed between the first and second pixels, wherein the first subpixel position is disposed approximately at a center of the first edge; 3) a third circuit for increasing a luminance value of a second subpixel disposed on a first side of the first edge center; and 4) a fourth circuit for decreasing a luminance value of a third subpixel disposed on a second side of the first edge center opposite the first side.

System and method for improving the sharpness of a video image

Methods and apparatus for viewing a secondary television program simultaneously with a primary program. The apparatus includes a receiver for receiving a primary program and one or more secondary programs transmitted by a transmission source; a monitor adapted to display at least one of the primary program and the secondary programs; and a handheld device adapted to display at least a portion of one of the primary program and the secondary programs, wherein the program displayed on the handheld device is that which is not displayed on the monitor.

Johan Janssen

Papers

Image interpolation and decimation using a continuously variable delay filter and combined with a polyphase filter

Video sample rate conversion to achieve 3-D effects

Heterogeneous multi-processor for the management of real-time video and graphics streams

System and method for improving the sharpness of a video image

Methods and apparatus for simultaneously viewing multiple television programs