The scaling of CMOS technology deep into the nanometer range has created challenges for the design of highperformance analog ICs The shrinking supply voltage and presence of mismatch and noise restrain the dynamic range, causing analog circuits to be large in area and have a high power consumption in spite of the process scaling Analog circuits based on time encoding [1], [2] and hybrid analog/digital signal processing [3] have been developed to overcome these issues Realizing analog circuit functionality with highly digital circuits results in more scalable design solutions that can achieve excellent performance This article reviews the basic principles of time encoding applied, in particular, to analog-to-digital converters (ADCs) based on voltage-controlled oscillators (VCOs), one of the most successful time-encoding techniques to date

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Time-Encoding Analog-to-Digital Converters: Bridging the Analog Gap to Advanced Digital CMOS-Part 1: Basic Principles

A novel direct resistive-sensor-to-digital readout circuit is presented, which achieves 16.1-bit ENOB while being very compact and robust. The highly digital time-based architecture employs a single voltage-controlled oscillator (VCO), counter, and digital feedback loop for the readout of an external single-ended highly nonlinear resistive sensor, such as an NTC thermistor. In addition to the inherent first-order noise shaping due to the oscillator, the second loop in SMASH configuration creates second-order noise shaping. Fabricated in 180-nm CMOS, the readout circuit achieves 16.1 bit of resolution for 1-ms conversion time and consumes only $171~\mu \text{W}$ , resulting in an excellent 2.4-pJ/c.s. FOMW for a resistive sensor interface while occupying only 0.064 mm 2. The specific closed-loop architecture tackles the VCO nonlinearity, achieving more than 14 bits of linearity. Multiple prototype chip samples have been measured in a temperature-controlled environment from −40 °C to 125 °C for the readout of commercial external NTC thermistors. A maximum temperature inaccuracy of 0.3 °C is achieved with only one-point trimming at room temperature. Since the circuit architecture decouples the sensor excitation from the feedback, high electromagnetic interference (EMI) immunity at the sensor node is demonstrated as well.

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A 16.1-bit Resolution 0.064-mm 2 Compact Highly Digital Closed-Loop Single-VCO-Based 1-1 Sturdy-MASH Resistance-to-Digital Converter With High Robustness in 180-nm CMOS

The evolution of electronics towards compact and highly energy-efficient systems requires joint efforts in developing both innovative system architectures and novel devices. Recent developments show that time-based sensor interfaces yield highly-digital architectures, which are compatible with advanced silicon CMOS at highly-scaled technology nodes. Advancements in CMOS time-based sensor interfaces show that new circuit techniques can help to increase performance and robustness. Furthermore, these architectures have successfully been implemented in carbon nanotube technology, a promising technology to further reduce the energy consumption in electronics. In addition, CNTs are excellent candidates to be functionalized as sensors, and can potentially improve the energy efficiency of sensors and sensor interfaces for future autonomy-demanding applications. This paper presents an overview of time-based sensor interfaces implemented in CMOS and CNT technologies, allowing for scalable and robust designs. Several CMOS and VLSI-compatible CNFET-based sensor interface circuits have been fabricated and validated through measurements, demonstrating the feasibility of these solutions.

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Time-Based Sensor Interface Circuits in CMOS and Carbon Nanotube Technologies

The scaling of CMOS technology deep into the nanometer range has created challenges for the design of highperformance analog ICs: they remain large in area and power consumption in spite of process scaling. Analog circuits based on time encoding [1], [2], where the signal information is encoded in the waveform transitions instead of its amplitude, have been developed to overcome these issues. While part one of this overview article [3] presented the basic principles of time encoding, this follow-up article describes and compares the main time-encoding architectures for analog-to-digital converters (ADCs) and discusses the corresponding design challenges of the circuit blocks. The focus is on structures that avoid, as much as possible, the use of traditional analog blocks like operational amplifiers (opamps) or comparators but instead use digital circuitry, ring oscillators, flip-flops, counters, an so on. Our overview of the state of the art will show that these circuits can achieve excellent performance. The obvious benefit of this highly digital approach to realizing analog functionality is that the resulting circuits are small in area and more compatible with CMOS process scaling. The approach also allows for the easy integration of these analog functions in systems on chip operating at "digital" supply voltages as low as 1V and lower. A large part of the design process can also be embedded in a standard digital synthesis flow.

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Time-Encoding Analog-to-Digital Converters: Bridging the Analog Gap to Advanced Digital CMOS?Part 2: Architectures and Circuits

Due to their high compatibility with scaled CMOS and emerging technologies, highly-digital time-based architectures, such as PLL-based architectures, have become an attractive alternative to amplitude-based circuits for sensor interfaces, in terms of high time resolution and the potential for low power and area scalability. Although quantization and thermal noise in PLL-based architectures can be addressed by applying noise shaping and oversampling, offset and 1/f noise limit the resolution at high oversampling ratios. Therefore, dynamic offset cancelation techniques such as chopping and autozeroing, as used in traditional amplitude-based circuits, must be adapted to such time-based implementations as well. This paper presents a digital-domain chopping technique suited for offset and 1/f-noise cancelation in applications where medium-to-high-resolution sensor interfaces are needed. System-level simulations demonstrate the benefits of this technique at high oversampling ratios. The resolution improvement is confirmed by measurements, showing the rate of 10 dB of SNR gain per decade of oversampling as expected from theory.

Digital-domain chopping technique for high-resolution PLL-based sensor interfaces ☆

This paper presents a drift-resilient time-based resistive sensor interface in a 0.18- $\mu \text{m}$ CMOS technology. The interface is built around only two oscillators, a phase detector, a digital filter, and a digital-to-analog converter (DAC), resulting in a simple first-order Delta–Sigma design with a predictable transfer function. The highly digital approach not only results in a small area but also implies that only a few analog circuits are sensitive to drift. The holistic drift-resilience strategy implemented combines time-based chopping and voltage-controlled oscillator (VCO) tuning to remove the dc and low-frequency errors introduced by VCO nonidealities and drift. These techniques do not introduce a significant area and power overhead. Silicon measurements show that the proposed bang–bang phase-locked loop (BBPLL)-based sensor interface exhibits ppm-level gain drift and offset drift for the entire −40 °C–175 °C temperature range while using a single-temperature calibration scheme and no external accurate references nor components for this drift stability. The interface provides a 15-effective number of bits conversion for a 100-ms conversion time and consumes 3.41 mW of power and occupies only 0.23 mm2 of the active area.

A Robust BBPLL-Based 0.18- $\mu$ m CMOS Resistive Sensor Interface With High Drift Resilience Over a −40 °C–175 °C Temperature Range

This paper presents a very-low-drift 0.181µ m CMOS time-based resistive-bridge sensor interface. It exhibits only 3.8 ppm/° C gain drift and 0.3 ppm/°C offset drift for the entire −40°C to 175°C temperature range using a single-temperature calibration scheme and no external accurate references nor components. The interface provides a 15 ENOB for a 100ms conversion time, consuming 3.41mW of power and 0.26mm2 of active area. The holistic drift-resilience strategy combines time-based chopping and VCO tuning to remove the DC and low-frequency errors introduced by VCO nonidealities and drift.

A Single-Temperature-Calibration 0.18-µm CMOS Time-Based Resistive Sensor Interface with Low Drift over a −40°C to 175°C Temperature Range

Sensor interface circuits are traditionally based on analog approaches. Recently, time-based architectures have become more popular thanks to their highly-digital scalable implementation. However, the poor VCO linearity limits the achievable overall linearity. This paper presents a novel single- VCO-based sensor interface architecture in closed-loop configuration, thus ensuring higher linearity. Models are proposed and analytic expressions are derived to estimate the sensor interface resolution based on the characteristics and noise performance of the single building blocks. Based on frequency-domain models, the STF and the NTF are derived for both the open-loop and the closed-loop configuration, and the SNR is calculated. The closed- loop architecture can achieve the same resolution as the open- loop one, provided that the feedback circuit noise is negligible compared to the other sources of noise, while ensuring a better linearity at the expense of lower speed and a small area and power overhead.

Johan Vergauwen

Papers

A 16.1-bit Resolution 0.064-mm 2 Compact Highly Digital Closed-Loop Single-VCO-Based 1-1 Sturdy-MASH Resistance-to-Digital Converter With High Robustness in 180-nm CMOS

Digital-domain chopping technique for high-resolution PLL-based sensor interfaces ☆

A Robust BBPLL-Based 0.18- $\mu$ m CMOS Resistive Sensor Interface With High Drift Resilience Over a −40 °C–175 °C Temperature Range

A Single-Temperature-Calibration 0.18-µm CMOS Time-Based Resistive Sensor Interface with Low Drift over a −40°C to 175°C Temperature Range

From Open-Loop to Closed-Loop Single-VCO-Based Sensor-to-Digital Converter Architectures: theoretical analysis and comparison