Customizable semiconductor devices, integrated circuit gate arrays and techniques to produce same are disclosed. The devices comprise integrated circuit blanks having a collection of semiconductor elements and at least one metal layer including fusible links interconnecting said collection of semiconductor elements into an inoperably connected integrated circuit blank. At least one metal layer is first etched thereby to define a pattern of conductors. A passivation layer is provided over at least one metal layer, afterwhich at least one metal layer is etched a second time for selectably removing the fusible links, thereby converting the inoperable integrated circuit blank into a selected operable electronic function.

Personalizable gate array devices

A wafer substrate for integrated circuits (1) which by itself may be made either of conductive or non-conductive material. This substrate carries two planes or layers of patterned metal (19, 20), thus providing two principal levels of interconnection. An insulation layer (21) is placed between the metal layers and also between the lower metal layer and the substrate if the latter is conductive. Connections between the metal layers or between the metal layer and the substrate can be made through via holes in the insulator layer or layers, respectively. The real estate provided by the substrate (1) is divided up into special areas used for inner cells (2) outer cells (3) signal hookup areas (4) and power hookup areas (5). The cells are intended to host the integrated circuit chips (24, 25) and to provide the bonding pads (8) for the signal connections between the chips and the substrate.

Universal interconnection substrate

The present invention relates to a signal driver circuit for driving a liquid crystal display panel. The signal driver circuit provides level shifting within the circuit to lower the power consumption of a liquid crystal display module while still providing a wide analog voltage range to the liquid crystal display elements. The decoding circuits utilize a strand of abutting decode input transistors which are connected in series. Further to reduce the physical size of the decoding circuits, multiple decode circuits may share circuitry that decodes the most significant bits of a data word. A cell layout is utilized such that the most significant bits data are bused into the cell through metal lines and the least significant bits are bused in polysilicon that also operates as the gate of the decode input transistors. Moreover, the decode cell input transistors may all be of the same conductivity type.

Signal driver circuit for liquid crystal displays

A selectably customizable semiconductor device including a first metal layer disposed in a first plane and including first elongate strips extending parallel to a first axis, a second metal layer disposed in a second plane generally parallel to and electrically insulated from the first plane and including second elongate strips extending parallel to a second axis, the second axis being generally perpendicular to the first axis, whereby a multiplicity of elongate strip overlap locations are defined at which the elongate strips of the first and second metal layers overlap in electrical insulating relationship, the first metal layer including a plurality of fusible conductive bridges joining adjacent pairs of the first elongate strips, the fusible conductive bridges including first and second fusible links, the first metal layer also including a plurality of branch strips, each branch strip connecting one of the fusible conductive bridges at a location intermediate the first and second fusible links to a branch overlap location spaced from the multiplicity of elongate strip overlap locations, an electrical connection being formed between the first metal layer and the second metal layer at each of the branch overlap locations.

Customizable semiconductor devices

An integrated circuit structure is described which includes a base semiconductor structure and a programmable semiconductor structure which are fabricated separately and later joined to form the integrated circuit structure The base semiconductor structure includes conventional semiconductor devices fabricated in accordance with a first set of design rules The programmable semiconductor structure includes programmable elements fabricated in accordance with a second set of design rules which may be different than the first set of design rules The programmable elements are used to control the configuration of the integrated circuit structure or to provide field programmable devices for use in the integrated circuit structure

Semiconductor device having programmable interconnect layers

Disclosed are improved LSI semiconductor design structures termed "Master Image Chip Organization Techniques". Utilizing the technique provides increased density and optimized performance of semiconductor devices, circuits, and part number functions. In accordance with the disclosed Master Image Chip Organization Method the semiconductor chips are optimally structured to facilitate the maximum number of devices and circuits, and to facilitate fabrication of a wide variety of LSI part numbers. Essentially, none of the semiconductor surface is dedicated for signal and power wiring channels. A master image wiring structure is provided which resides over the semiconductor surface and beneath a power surface. In addition, the master image wiring structure provides a means for personalizing power and signal wiring for a multiple power surface structure. The combined master image structure provides a means for optimally allocating semiconductor area for devices, functional units (micro and macro) and signal and power wiring to facilitate improved density and performance.

Master image chip organization technique or method

Disclosed is an improved masterslice design tech-nique including structure, wiring, and method of fabricating, to provide improved Large Scale Inte-grated Devices. In accordance with the improved masterslice tech-nique a plurality of semiconductor chips are pro-vided wherein essentially the entire semiconductor surface area of each chip is utilized to provide cells selectable to be personalized (wired). None of the semiconductor surface area is dedicated for wiring channels. The individual cell area and cell configuration is optimally arrived at to facilitate wiring the maximum number, if not all of the cells contained on each chip, whereby circuit density is materially improved and a wide variety LSI device part numbers may be readily fabricated.

Lsi semiconductor device and fabrication thereof

Bei einer hochintegrierten Halbleiterschaltung, basierend auf dem Master-Slice-Prinzip, mit in einem Halbleiterchip (1) integrierten und gegeneinander isolierten Bauelementen, die uber mehrere Verdrahtungsebenen entsprechend einer vorgegebenen Funktion verbunden sind, werden die Bauelemente in einer Matrix aus Spalten (C) und Zeilen (R) von gegeneinander isolierten Einheitszellen (F) angeordnet. In a highly integrated semiconductor circuit based on the master slice principle, with a semiconductor chip (1) integrated and mutually insulated components, which are connected via a plurality of wiring planes in accordance with a predetermined function, the components are in a matrix of columns (C) and rows (R) of mutually insulated unit cells (F) arranged. Im wesentlichen wird die gesamte Halbleiteroberflache mit Ausnahme von Isolationsbereichen zwischen den Zellen und einem Grenzbereich von eingeschrankter Breite am Umfang des Chips fur diese Zellen verwendet. Substantially the entire semiconductor surface, with the exception of isolation regions between the cells and a boundary region of reduced width at the periphery of the chip is used for these cells. Bis auf eine begrenzte Anzahl haben alle Zellen die gleiche Konfiguration, den gleichen Komponenteninhalt und sie belegen die gleiche Chipflache. Except for a limited number of all cells have the same configuration, the same components content and they occupy the same chip area. Die Mehrzahl der Zellen ist in Bundeln von Zellen (F1, F2, F3, F4) so angeordnet, das jede Zelle eine eindeutige geometrische Orientierung zu den ubrigen Zellen ihres Bundels hat. The plurality of cells is arranged in bundles of cells (F1, F2, F3, F4) so ​​that each cell has a unique geometric orientation with respect to the other cells of its bundle.

Large scale integrated circuit and method of fabricating the same

A method and apparatus for storing in a read only memory a matrix having one or more rows each with a majority of '''' 1'''' bits. There is formed the complement of each of those rows having a majority of '''' 1'''' bits to form a new matrix wherein no row has a majority of '''' 1'''' bits. The new matrix is stored in a read only memory. Upon reading out one or more rows of the matrix the bits of the complemented rows are reinverted.

Read only memory and method of using same

A symmetrical direct-coupled trigger circuit comprising first and second interconnected stages, each including current switch logic means. In the first stage, a plurality of current switches have selected respective collector output lines and emitter output lines interconnected to provide logic signals at a pair of nodes; the nodes are connected to the second stage so that accompanying signal propogation is held to two stages of delay.

John A. Palmieri

Papers

Master image chip organization technique or method

Lsi semiconductor device and fabrication thereof

Large scale integrated circuit and method of fabricating the same

Read only memory and method of using same

Direct-coupled trigger circuit