T
Teh-Sen Jen
Researcher at IBM
Publications - 5
Citations - 110
Teh-Sen Jen is an academic researcher from IBM. The author has contributed to research in topics: Electronic circuit & Semiconductor. The author has an hindex of 4, co-authored 5 publications receiving 110 citations.
Papers
More filters
Patent
Master image chip organization technique or method
John Balyoz,Chi S. Chang,Barry C. Fox,John A. Palmieri,Majid Ghafghaichi,Teh-Sen Jen,Donald B. Mooney +6 more
TL;DR: In this paper, a master image wiring structure is provided which resides over the semiconductor surface and beneath a power surface, and the combined master image structure provides a means for optimally allocating semiconductor area for devices, functional units and signal and power wiring to facilitate improved density and performance.
Patent
Lsi semiconductor device and fabrication thereof
John Balyoz,Chi S. Chang,Barry C. Fox,Majid Ghafghaichi,Teh-Sen Jen,Donald B. Mooney,John A. Palmieri +6 more
TL;DR: In this paper, an improved masterslice design tech-nique including structure, wiring, and method of fabricating, to provide improved Large Scale Inte-grated Devices is presented.
Patent
High density semiconductor integrated circuit layout
TL;DR: In this article, an integrated logic circuit having a novel layout in a semiconductor substrate is presented, where the area required for the circuits within the substrate is substantially less than that of prior layouts.
Patent
Large scale integrated circuit and method of fabricating the same
John Balyoz,Chi S. Chang,Barry C. Fox,Majid Ghafghaichi,Teh-Sen Jen,Donald B. Mooney,John A. Palmieri +6 more
TL;DR: In this paper, the authors describe a Hochintegrierten Halbleiterschaltung, based on the master slice principle, with a semiconductor chip (1) integrated and mutually insulated components, which are connected via a plurality of wiring planes in accordance with a predetermined function, the components are in a matrix of columns (C) and rows (R) of mutually insulated unit cells arranged.
Patent
High density semiconductor circuit layout
TL;DR: In this article, an integrated logic circuit having a novel layout in a semiconductor substrate is presented, where each circuit includes a first device including an elongated impurity region and a set of other impurity regions either in, or in contiguous relationship with, the elongated region.