Limiting the energy consumption of computers, especially portables, is becoming increasingly important. Thus, new energy-saving computer components and architectures have been and continue to be developed. Many architectural features have both high-performance and low-power modes, with the mode selection under software control. The problem is to minimize energy consumption while not significantly impacting the effective performance. We group the software control issues as follows: transition, load-change, and adaptation. The transition problem is deciding when to switch to low-power, reduced-functionality modes. The load-change problem is determining how to modify the load on a component so that it can make further use of its low-power modes. The adaptation problem is determining how to create software that allows components to be used in novel, power-saving ways. We survey implemented and proposed solutions to software energy management issues created by existing and suggested hardware innovations.

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Software strategies for portable computer energy management

Si metal-oxide-semiconductor field-effect transistor (MOSFET) scaling trends are presented along with a description of today's 0.13-/spl mu/m generation transistors. Some of the foreseen limits to future scaling include increased subthreshold leakage, increased gate oxide leakage, increased transistor parameter variability and interconnect density and performance. Basic device and circuit requirements for electronic logic and memory products are described. These requirements need to be kept in mind when evaluating nanotechnology options such as carbon nanotube field-effect transistors (FETs), nanowire FETs, single electron transistors and molecular devices as possible future replacements for Si MOSFETs.

Nanotechnology goals and challenges for electronic applications

Impact on parametric performance of physical design choices for transistors is scored for on-current and off-current of the transistors. The impact of the design parameters are incorporated into parameters that measure predicted shift in mean on-current and mean off-current and parameters that measure predicted increase in deviations in the distribution of on-current and the off-current. Statistics may be taken at a cell level, a block level, or a chip level to optimize a chip design in a design phase, or to predict changes in parametric yield during manufacturing or after a depressed parametric yield is observed. Further, parametric yield and current level may be predicted region by region and compared with observed thermal emission to pinpoint any anomaly region in a chip to facilitate detection and correction in any mistakes in chip design.

Methods and system for analysis and management of parametric yield

We demonstrate that the temperature at which the C49 TiSi2 phase transforms to the C54 TiSi2 phase can be lowered more than 100 °C by alloying Ti with small amounts of Mo, Ta, or Nb. Titanium alloy blanket films, containing from 1 to 20 at. % Mo, Ta, or Nb were deposited onto undoped polycrystalline Si substrates. The temperature at which the C49–C54 transformation occurs during annealing at constant ramp rate was determined by in situ sheet resistance and x-ray diffraction measurements. Tantalum and niobium additions reduce the transformation temperature without causing a large increase in resistivity of the resulting C54 TiSi2 phase, while Mo additions lead to a large increase in resistivity. Titanium tantalum alloys were also used to form C54 TiSi2 on isolated regions of arsenic doped Si(100) and polycrystalline Si having linewidths ranging from 0.13 to 0.56 μm. The C54 phase transformation temperature was lowered by over 100 °C for both the blanket and fine line samples. As the concentration of Mo, Ta...

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Low temperature formation of C54–TiSi2 using titanium alloys

High battery lifetime is important to the usabil-ity and acceptance of portable computers. In order to develop strategies to minimize power consumption , designers need a good picture of the total power consumption of a system. For this purpose , we indicate the power consumptions of a set of portable computers and how they are broken down among the components of those computers. Then, we use user prooles to show how the use of power-saving features currently implemented serves to reduce these power consumptions by 35{56%. We also show how these power-saving features aaect the breakdown of overall power consumption, so that we can evaluate how successful certain new software techniques and hardware changes would be at reducing power consumption. The results of this paper point out the most promising avenues for further work in the reduction of power consumption, and indicate some strategies that can provide an immediate power beneet to the class of machines studied.

A complete picture of the energy consumption of a portable computer

Test circuits and methods for accurately flagging out-of-spec resistance in a current carrying structure of an integrated circuit employ a plurality of monitor structures connected in parallel and a test means for monitoring the monitor structures. Each monitor structure includes a test structure and an associated threshold sensitive device. Each test structure is predesigned relative to the current carrying structure of the integrated circuit such that an out-of-spec resistance in the test structure signals a possible out-of-spec resistance in the current carrying structure. The threshold sensitive device of each monitor structure outputs a fail signal when resistance of the associated test structure is above a predefined level. The fail signal is representative of an out-of-spec resistance in the associated test structure and flags possible out-of-spec resistance in the current carrying structure. The test means simultaneously monitors the plurality of monitor structures for a fail signal. An automated test device is also disclosed for providing a binary count representative of a total number of out-of-spec test structures.

Fabrication test circuit and method for signalling out-of-spec resistance in integrated circuit structure

A method of performing model to hardware correlation that simulates models based upon design criteria and manufactures devices based upon the design criteria. The method evaluates features of the devices during the manufacturing to produce in-line test parametric data, compares the models to the in-line test parametric data to obtain correlation data, and modifies the simulating according to the correlation data.

Method and system for including parametric in-line test data in simulations for improved model to hardware correlation

http://www.qed2.com/uploads/3/5/3/7/3537200/miles1996.pdf

TiSi2 phase transformation characteristics on narrow devices

An experimental 2.0 V PowerPC 601 microprocessor demonstrating 3/spl times/ active power reduction and performance comparable to the 3.6 V version has been fabricated. The standard 3.6 V 0.6 /spl mu/m CMOS technology was modified for low-power operation with unmodified circuits/masks. No degradation to yield was observed. Experimental low-voltage PowerPC 601 process/device alterations and test results are described. >

Experimental 2.0 V power/performance optimization of a 3.6 V-design CMOS microprocessor-PowerPC 601

An experimental 2.0*volt low-power PowerPC 601TM Microprocessor built In a modified 3.6-volt, 0.6-tim IBiUI CMOS technology Is described. By using unmodified masks from the 3.6-volt design, a 3x power savings was realized while maintaining nearly the original performance. The use of selective scaling provides high performance at reduced power supply voltage. This technique, applicable to selected existing product designs, may allow early entry into the low-power marlcet while minimizing new process development expense. The technique proposes hyperscaled reductions in specific electrical and physical parameters, while keeping horizontal layout rules unchanged. Static chip designs, which comprise the majority of 601 circuitry, respond well to the alterations. In addition, potential reliability detractors are reduced or eliminated. Challenges to this technique include I/O Interfacing and minimizing leakages associated with low device thresholds. The 601 design and its base technology are described, along with the experimental changes. The paper reviews the motivation behind lowpower microprocessor development, alternative power-saving techniques being practiced, and opportunities for continued power reduction.

John E. Bertsch

Papers

Fabrication test circuit and method for signalling out-of-spec resistance in integrated circuit structure

Method and system for including parametric in-line test data in simulations for improved model to hardware correlation

TiSi2 phase transformation characteristics on narrow devices

Experimental 2.0 V power/performance optimization of a 3.6 V-design CMOS microprocessor-PowerPC 601

Reduced-voltage power/performance optimization of the 3.6-volt PowerPC 601 Microprocessor