An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

A programmable logic array integrated circuit has a number of programmable logic modules which are grouped together in a plurality of logic array blocks ("LABs"). The LABs are arranged on the circuit in a two dimensional array. A conductor network is provided for interconnecting any logic module with any other logic module. In addition, adjacent or nearby logic modules are connectable to one another for such special purposes as providing a carry chain between logic modules and/or for connecting two or more modules together to provide more complex logic functions without having to make use of the general interconnection network. Another network of so-called fast or universal conductors is provided for distributing widely used logic signals such as clock and clear signals throughout the circuit. Multiplexers can be used in various ways to reduce the number of programmable interconnections required between signal conductors.

Programmable logic array integrated circuits

A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications. A plurality of user-configurable interconnect elements are placed directly between the second and third interconnect layers at the intersections of selected segments of the segmented conductors in the second and third interconnect layers. More user-configurable interconnect elements are located between adjacent segments of the segmented conductors in both the second and third interconnect layers. Pass transistors located in the semiconductor substrate in between the functional circuit modules are connected between adjacent segments in both the second and third interconnect layers and between selected intersecting segments in the second and third interconnect layers.

Programmable interconnect architecture

An improved programmable logic cell (1) for use in a programmable logic array comprising cells which are arranged in two-dimensional matrix of rows and columns and are interconnected by a two-dimensional array of direct connections between a cell (1) and its four nearest neighbors, one to its left (or to the West) (3a, 3b, 7a, 7b) and one to its right (or to the East) (5a, 5b, 9a, 9b), one above it (or to the North) (2a, 2b, 6a, 6b) and one below it (or to the South) (4a, 4b, 8a, 8b). Each cell receives input (s) from each of its nearest neighbors and additional input(s) from a bus, pin, or neighbor and may be programmed to generate a variety of logical functions at its outputs which connect to the cell's four nearest neighbors. The core of the improved logic cell (fig.2) comprises two upstream gates (21, 23) the outputs of which feed two downstream gates (28, 41), one of which is an exclusive-OR gate (28) which feeds a downstream register (33). Additional programmable connections and other logic augment the cell core to produce cell embodiments which can be configured to efficiently implement various logical functions. Among the functions which may be implemented by the improved cell are a number of two-level combinational functions (such as multiplexing) and sequential functions (such as counting and shifting). A variety of cell embodiments based on the improved cell core are illustrated.

Programmable logic cell and array

In an aspect, an apparatus is provided that sets and reprograms the state of programmable devices. In an aspect, a method is provided such that an opening is formed through a dielectric exposing a contact, the contact formed on a substrate. An electrode is conformally deposited on a wall of the dielectric, utilizing atomic layer deposition (ALD). A programmable material is formed on the electrode and a conductor is formed to the programmable material. In an aspect, a barrier is conformally deposited utilizing ALD, between the electrode and the programmable material.

Utilizing atomic layer deposition for programmable device

A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Programmable application specific integrated circuit and logic cell therefor

A programmable logic array (100) includes a set of input terms which are programmably coupled to a first set of AND gates (102-1 through 102-66). The output signals from the first set of AND gates are programmably elec­trically connected to a second set of AND gates (104-1 through 104-66). The second set of programmable AND gates enhances flexibility of design and permits product terms with a larger number of factors to be generated. The output leads from the second set of AND gates are programmably electrically coupled to a first set of OR gates (106-1 through 106-22) which in turn are program­mably electrically coupled to a second array of OR gate logic (108-1 through 108-10). This also permits greater design flexibility. The output terms from the second set of OR gate logic can then be used to generate the output signals from the programmable logic array (100). In addition, a bus (110) is programmably electrically coup­led to each of the output signals from the second OR logic array and the output pins (O₁ through O₁₀) of the PLA. Because of this, different output terms can be routed to different output pins thus permitting the designer to select his pin out independently of the availability of gate within specific parts of the array.

Programmable logic array with added array of gates and added output routing flexibility

In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C, or reactively sputtered in a variety of reactive gases In another method, an oxide layer is placed between two amorphous silicon film layers In yet another method, one of the amorphous silicon film layers about the oxide layer is doped In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage A method also is described for for forming a field programmable gate array with antifuses

Method for fabrication of programmable interconnect structure

A programmable array logic cell (60) including a sum-of- products array having a single OR gate (70) for providing a sum signal, and including an XOR gate (80) for combining the sum signal with a product signal provided by an AND gate (78) from selected array input and/or feedback signals. The product signal can be the previous state output signal Q for a JK flip flop configuration, or a forced high or low signal for other configurations for programmable output signal polarity.

Programmable array logic cell

In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

John M. Birkner

Papers

Programmable application specific integrated circuit and logic cell therefor

Programmable logic array with added array of gates and added output routing flexibility

Method for fabrication of programmable interconnect structure

Programmable array logic cell

Electrically programmable interconnect structure having a PECVD amorphous silicon element