A user-configurable circuit architecture includes a two dimensional array of functional circuit modules disposed within a semiconductor substrate. A first interconnect layer disposed above and insulated from the semiconductor substrate contains a plurality of conductors and is used for internal connections within the functional circuit modules. A second interconnect layer disposed above and insulated from the first interconnect layer contains a plurality of segmented tracks of conductors running in a first direction and is used to interconnect functional circuit module inputs and outputs. A third interconnect layer disposed above and insulated from the second interconnect layer contains a plurality of segmented tracks of conductors running in a second direction, some of the segments of conductors forming intersections with ones of the segments of the conductors in the second interconnect layer, and is used to interconnect functional circuit module inputs and outputs to implement the desired applications. A plurality of user-configurable interconnect elements are placed directly between the second and third interconnect layers at the intersections of selected segments of the segmented conductors in the second and third interconnect layers. More user-configurable interconnect elements are located between adjacent segments of the segmented conductors in both the second and third interconnect layers. Pass transistors located in the semiconductor substrate in between the functional circuit modules are connected between adjacent segments in both the second and third interconnect layers and between selected intersecting segments in the second and third interconnect layers.

Programmable interconnect architecture

A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Programmable application specific integrated circuit and logic cell therefor

A programmable logic device having a rela­tively small number of programmable product terms (OE,SETN,P0,P1,P2,INV,ACLK,CLEARN) ("P-terms") feeding each fixed combinatorial logic device (51), and additional "expander" programmable P-terms (EXP1,EXP2) which do not directly feed a fixed device. Relatively simple logic functions can be performed by suitably programming the P-terms feeding the fixed devices. More complex logic functions can be performed by suitably programming the required number of expander P-terms, and then combining the outputs of those P-terms by means of another P-term. In addition, a programmable interconnect array (60) is provided to allow certain inputs (40) to the device to be applied to any programmable portion of the device, and also to allow the outputs of at least one of the fixed devices to be also applied to any programmable portion of the device.

Programmable logic device with array blocks connected via a programmable interconnect array

The configurable processor system includes a processor, an internal system bus, and a programmable logic all interconnected via the internal system bus, on a single integrated circuit.

Configurable processor system unit

A logic module includes first and second multiplexers each having two data inputs and a select input. Both select inputs are connected to the output of a two-input logic gate of a first type. The inputs to the first and second multiplexers comprise data signals from a first group. One input of each logic gate comprises a data signal of a second group and the other input of each logic gate comprises a data signal of a third group. A third multiplexer has first and second data inputs connected the outputs of the first and second multiplexers, respectively, and a select input connected to the output of a two-input logic gate of a second type. Its output is connected to a first data input of a fourth multiplexer having a HOLD1 input coupled to its select input. Its output and a CLEAR input are presented to an AND gate whose output is connected to the second data input of the fourth multiplexer and to the first data input of a fifth multiplexer. The fifth multiplexer select input comprises a HOLD2 input. Its output and the CLEAR input are presented to an AND gate whose output is connected to the second data input of the fifth multiplexer and to an output node. The CLEAR, HOLD1 and HOLD2 inputs comprise combinations of signals from a data signal of a third group which may contain data signals of one of the other groups.

Logic module with configurable combinational and sequential blocks

A programmable array logic cell (60) including a sum-of- products array having a single OR gate (70) for providing a sum signal, and including an XOR gate (80) for combining the sum signal with a product signal provided by an AND gate (78) from selected array input and/or feedback signals. The product signal can be the previous state output signal Q for a JK flip flop configuration, or a forced high or low signal for other configurations for programmable output signal polarity.

Programmable array logic cell

An output circuit (50) is provided for a programmable logic array (PLA) integrated circuit. The output circuit (50) includes a flip flop (52) which stores a given output term from the array. The flip flop (52) contains a set input lead (S) and a reset input lead (R). The signals present at the set input, reset input, and clock leads are generated by programmable logic within the PLA. A multiplexer (54) is provided which receives the output data of the flip flop (52) and the signal constituting the input data for the flip flop. The multiplexer provides the data input signal on the multiplexer output lead (60) when both the set and reset input signals are true. However, if either or both the set and reset input signals are false, then the multiplexer (54) provides the Q output signal from the flip flop (52) on the multiplexer output lead (60). The multiplexer output signal is presented to a three-state buffer (62) which in turn drives an output pin.

Output circuit for a programmable logic array

A programmable array logic circuit is provided having a programmable AND gate array and having means for connecting individual AND gate outputs to the input of one or the other of a pair of neighboring OR gates This allows the product terms to be shared between two outputs

Sing Y. Wong

Papers

Programmable array logic cell

Output circuit for a programmable logic array

Programmable array logic circuit with shared product terms