J
John T. Moore
Researcher at Micron Technology
Publications - 113
Citations - 3661
John T. Moore is an academic researcher from Micron Technology. The author has contributed to research in topics: Layer (electronics) & Substrate (electronics). The author has an hindex of 30, co-authored 113 publications receiving 3661 citations.
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Patent
PCRAM cell manufacturing
John T. Moore,Terry L. Gilton +1 more
TL;DR: In this paper, the authors present a method for forming a programmable cell by forming an opening in a dielectric material to expose a portion of an underlying first conductive electrode, forming a recessed chalcogenide-metal ion material in the opening and forming a second conductive electrodes overlying the dielectrics and the chalcanogenide metal ion material.
Patent
Apparatus and method for dual cell common electrode PCRAM memory device
TL;DR: In this article, two PCRAM cells which use a common anode between them are disclosed, and two memory cells can be accessed separately to store two bits of data which can be read and written.
Patent
Films doped with carbon for use in integrated circuit technology
Ronald A. Weimer,John T. Moore +1 more
TL;DR: The use of the films in integrated circuit technology, such as capacitors, DRAM constructions, semiconductive material assemblies, etching processes, and methods for forming capacitors and DRAMs was discussed in this article.
Patent
Silver-selenide/chalcogenide glass stack for resistance variable memory
Kristy A. Campbell,John T. Moore +1 more
TL;DR: In this paper, a resistance variable memory element is provided having at least one silver-selenide layer (18) in between glass layers(17, 20, 21) and a chalcogenide glass, preferably having GexSe100-x composition.
Patent
Electroless plating of metal caps for chalcogenide-based memory devices
TL;DR: In this article, a method of forming a metal cap over a conductive interconnect in a chalcogenide-based memory device is presented, which includes, forming a layer of a first conductive material (21) over a substrate (10), depositing an insulating layer (20) over the substrate, forming an opening (22) in the insulating layers to expose at least a portion of the first conductivity, depositing a second conductivity material (30) over this opening and within the opening, removing portions of the second conductiveness, rec