We investigate the effects of length (<inline-formula> <tex-math notation="LaTeX">${L}$ </tex-math></inline-formula>) and width (<inline-formula> <tex-math notation="LaTeX">${W}$ </tex-math></inline-formula>) scaling on the low-frequency noise characteristics of the ferroelectric tunnel junction (FTJ). The FTJ is composed of metal/ferroelectric/dielectric/semicondu- ctor (TiN/HfZrO2/SiO2/<inline-formula> <tex-math notation="LaTeX">${n}^{+}$ </tex-math></inline-formula> Si). In the high-resistance state, 1/<inline-formula> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> noise increases proportionally to 1/<inline-formula> <tex-math notation="LaTeX">${W}^{\alpha }{L}^{\beta }$ </tex-math></inline-formula> (<inline-formula> <tex-math notation="LaTeX">$\alpha \cong ~1$ </tex-math></inline-formula>, <inline-formula> <tex-math notation="LaTeX">$\beta >1$ </tex-math></inline-formula>), whereas the shot noise has no scaling dependence. In the low-resistance state, the 1/<inline-formula> <tex-math notation="LaTeX">${f}$ </tex-math></inline-formula> noise of the FTJ shows a more sensitive dependence on <inline-formula> <tex-math notation="LaTeX">${L}$ </tex-math></inline-formula> scaling than <inline-formula> <tex-math notation="LaTeX">${W}$ </tex-math></inline-formula> scaling since the switching and conduction mechanisms are more affected by the process-induced damaged edge regions.

Investigation of Low-Frequency Noise Characteristics of Ferroelectric Tunnel Junction: From Conduction Mechanism and Scaling Perspectives

Gaseous pollutants, including nitrogen oxides, pose a severe threat to ecosystems and human health; therefore, developing reliable gas-sensing systems to detect them is becoming increasingly important. Among the various options, metal-oxide-based gas sensors have attracted attention due to their capability for real-time monitoring and large response. In particular, in the field of materials science, there has been extensive research into controlling the morphological properties of metal oxides. However, these approaches have limitations in terms of controlling the response, sensitivity, and selectivity after the sensing material is deposited. In this study, we propose a novel method to improve the gas-sensing performance by utilizing the remnant polarization of ferroelectric thin-film transistor (FeTFT) gas sensors. The proposed FeTFT gas sensor has IGZO and HZO as the conducting channel and ferroelectric layer, respectively. It is demonstrated that the response and sensitivity of FeTFT gas sensors can be modulated by engineering the polarization of the ferroelectric layer. The amount of reaction sites in IGZO, including electrons and oxygen vacancy-induced negatively charged oxygen, is changed depending on upward and downward polarization. The results of this study provide an essential foundation for further development of gas sensors with tunable sensing properties.

Synergistic improvement of sensing performance in ferroelectric transistor gas sensors using remnant polarization.

We propose a hybrid self-curing method based on the parasitic bipolar junction transistor (PBJT) inherent to metal-oxide-semiconductor field-effect transistor (MOSFET). The PBJT utilizes the positive feedback of impact ionization to flow a large current close to the channel, generating Joule heat. Unlike conventional self-curing methods, the PBJT-based self-curing recovers the damaged gate oxide along the lateral dimension of the entire channel. The effects of the hybrid curing are quantitatively verified by low-frequency noise spectroscopy and charge pumping method. 

Highly Efficient Self-Curing Method in MOSFET Using Parasitic Bipolar Junction Transistor

We propose a hybrid self-curing method based on the parasitic bipolar junction transistor (PBJT) inherent to metal-oxide-semiconductor field-effect transistor (MOSFET). The PBJT utilizes the positive feedback of impact ionization to flow a large current close to the channel, generating Joule heat. Unlike conventional self-curing methods, the PBJT-based self-curing recovers the damaged gate oxide along the lateral dimension of the entire channel. The effects of the hybrid curing are quantitatively verified by low-frequency noise spectroscopy and charge pumping method.

We demonstrate that the resistance switching (RS) of an undoped hafnium oxide (HfOx)-based ferroelectric tunnel junction (FTJ) is affected not only by ferroelectric domain switching of HfOx but also by the redistribution of oxygen vacancies inside HfOx, known as the working principle of resistive random-access memory. It is revealed that the RS mechanism varies depending on the program bias applied to FTJ. Through low-frequency noise spectroscopy, a precise method for distinguishing two distinct RS processes intrinsic to FTJ is presented. 

Unveiling Resistance Switching Mechanisms in Undoped HfOx Ferroelectric Tunnel Junction Using Low-Frequency Noise Spectroscopy

Recently, ferroelectric tunnel junctions (FTJs) have gained extensive attention as possible candidates for emerging memory and synaptic devices for neuromorphic computing. However, the working principles of FTJs remain controversial despite the importance of understanding them. In this study, we demonstrate a comprehensive and accurate analysis of the working principles of a metal-ferroelectric-dielectric-semiconductor stacked FTJ using low-frequency noise (LFN) spectroscopy. In contrast to resistive random access memory, the 1/f noise of the FTJ in the low-resistance state (LRS) is approximately two orders of magnitude larger than that in the high-resistance state (HRS), indicating that the conduction mechanism in each state differs significantly. Furthermore, the factors determining the conduction of the FTJ in each state are revealed through a systematic investigation under various conditions, such as varying the electrical bias, temperature, and bias stress. In addition, we propose an efficient method to decrease the LFN of the FTJ in both the LRS and HRS using high-pressure forming gas annealing.

Comprehensive and accurate analysis of the working principle in ferroelectric tunnel junctions using low-frequency noise spectroscopy.

A gated diode with a charge trap insulator stack (Al2O3/Si3N4/SiO2) is proposed as a synaptic device and its potentiation and depression operations have been demonstrated. Using the band-to-band tunneling current, the gated diode operates with low current (in nanoampere range) and is suitable for low-power hardware-based neural networks. Since the proposed device has merits on simple and compact structure (half of a MOSFET) and compatibility with conventional CMOS technology, integration with CMOS peripheral circuits including neuron circuits and driving IC is possible.

CMOS-Compatible Low-Power Gated Diode Synaptic Device for Hardware- Based Neural Network

We propose a selective 1-bit soft erase scheme in vertical NAND (V-NAND) flash memory that improves retention characteristics. Selective 1-bit erase using gate-induced drain leakage (GIDL) is applied after program operation to remove shallowly trapped electrons. Compared to conventional methods, the proposed method improves retention characteristics by ~40% and the distribution of $\Delta V_{\text {th}}$ is narrowed to less than 30%. The proposed $V_{\text {th}}$ tuning scheme accurately adjusts $V_{\text {th}}$ to the target $V_{\text {th}}$, thereby improving the error rate of convolutional neural networks (CNNs) for image classification by 17% by adopting the 1-bit soft erase scheme.

Retention Improvement in Vertical NAND Flash Memory Using 1-bit Soft Erase Scheme and its Effects on Neural Networks

Artificial Neural Networks (ANNs) have shown remarkable performance in various fields. However, ANN relies on the von-Neumann architecture, which consumes a lot of power. Hardware-based spiking neural networks (SNNs) inspired by a human brain have become an alternative with significantly low power consumption. In this paper, we propose on-chip trainable SNNs using a time-to-first-spike (TTFS) method. We modify the learning rules of conventional SNNs using TTFS to be suitable for on-chip learning. Vertical NAND flash memory cells fabricated by a device manufacturer are used as synaptic devices. The entire learning process considering the hardware implementation is also demonstrated. The performance of the proposed network is evaluated through the MNIST classification in system-level simulation using Python. The proposed SNNs show an accuracy of 96% for a network size of 784 – 400 – 10. We also investigate the effect of non-ideal cell characteristics (such as pulse-to-pulse and device-to-device variations) on inference accuracy. Our networks demonstrate excellent immunity for various device variations compared with the networks using off-chip training.

https://ieeexplore.ieee.org/ielx7/6287639/9668973/09737122.pdf

Joon Hwang

Papers

Comprehensive and accurate analysis of the working principle in ferroelectric tunnel junctions using low-frequency noise spectroscopy.

CMOS-Compatible Low-Power Gated Diode Synaptic Device for Hardware- Based Neural Network

Highly Efficient Self-Curing Method in MOSFET Using Parasitic Bipolar Junction Transistor

Retention Improvement in Vertical NAND Flash Memory Using 1-bit Soft Erase Scheme and its Effects on Neural Networks

On-Chip Trainable Spiking Neural Networks Using Time-To-First-Spike Encoding