In this article, we present a small, complete, and efficient SAT-solver in the style of conflict-driven learning, as exemplified by Chaff. We aim to give sufficient details about implementation to enable the reader to construct his or her own solver in a very short time.This will allow users of SAT-solvers to make domain specific extensions or adaptions of current state-of-the-art SAT-techniques, to meet the needs of a particular application area. The presented solver is designed with this in mind, and includes among other things a mechanism for adding arbitrary boolean constraints. It also supports solving a series of related SAT-problems efficiently by an incremental SAT-interface.

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An Extensible SAT-solver

Symbolic model checking with Binary Decision Diagrams (BDDs) has been successfully used in the last decade for formally verifying finite state systems such as sequential circuits and protocols. Since its introduction in the beginning of the 90's, it has been integrated in the quality assurance process of several major hardware companies. The main bottleneck of this method is that BDDs may grow exponentially, and hence the amount of available memory re- stricts the size of circuits that can be verified efficiently. In this article we survey a technique called Bounded Model Checking (BMC), which uses a propositional SAT solver rather than BDD manipulation techniques. Since its introduction in 1999, BMC has been well received by the industry. It can find many logical er- rors in complex systems that can not be handled by competing techniques, and is therefore widely perceived as a complementary technique to BDD-based model checking. This observation is supported by several independent comparisons that have been published in the last few years.

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Bounded Model Checking

Besides Equivalence Checking [KK97, KPKG02] the most important industrial application of SAT is currently Bounded Model Checking (BMC) [BCCZ99]. Both techniques are used for formal hardware verification in the context of electronic design automation (EDA), but have successfully been applied to many other domains as well. In this chapter, we focus on BMC. In practice, BMC is mainly used for falsification resp. testing, which is concerned with violations of temporal properties. However, the original paper on BMC [BCCZ99] already discussed extensions that can prove properties. A considerable part of this chapter discusses these complete extensions, which are often called “unbounded” model checking techniques, even though they are build upon the same principles as plain BMC. Two further related applications, in which BMC becomes more and more important, are automatic test case generation for closing coverage holes, and disproving redundancy in designs. Most of the techniques discussed in this chapter transfer to this more general setting as well, even though our focus is on property verification resp. falsification. The basic idea of BMC is to represent a counterexample-trace of bounded length symbolically and check the resulting propositional formula with a SAT solver. If the formula is satisfiable and thus the path feasible, a satisfying assignment returned by the SAT solver can be translated into a concrete counterexample trace that shows that the property is violated. Otherwise, the bound is increased and the process repeated. Complete extensions to BMC allow to stop this process at one point, with the conclusion that the property cannot be violated, hopefully before the available resources are exhausted.

Bounded Model Checking.

Temporal Induction by Incremental SAT Solving

Dramatic improvements in SAT solver technology over the last decade and the growing need for more efficient and scalable verification solutions have fueled research in verification methods based on SAT solvers. This paper presents a survey of the latest developments in SAT-based formal verification, including incomplete methods such as bounded model checking and complete methods for model checking. We focus on how the surveyed techniques formulate the verification problem as a SAT problem and how they exploit crucial aspects of a SAT solver, such as application-specific heuristics and conflict-driven learning. Finally, we summarize the noteworthy achievements in this area so far and note the major challenges in making this technology more pervasive in industrial design verification flows.

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A survey of recent advances in SAT-based formal verification

We introduce SATIRE, a new satisfiability solver that is particular-ly suited to verification and optimization problems in electronic de-sign automation. SATIRE builds on the most recent advances in satisfiability research, and includes two new features to achieve even higher performance: a facility for incrementally solving sets of related problems, and the ability to handle non-CNF constraints. We provide experimental evidence showing the effectiveness of these additions to classical satisfiability solvers.

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SATIRE: a new incremental satisfiability engine

The Boolean satisfiability problem (SAT) has various applications in electronic design automation (EDA) fields such as testing, timing analysis and logic verification. SAT has been typically applied to EDA as follows: (1) formulation of the given problem as a SAT instance (2) solution of the SAT instance. In this paper we present a method to simultaneously solve several closely related SAT instances using incremental satisfiability (ISAT). In ISAT, the decision sequence made for a "prefix" function is used to solve another set of functions which have a number of new constraints (extensions) added to the prefix function. Our experiments show that we can achieve significant gains in total runtime when we use this methodology as opposed to resetting the decision sequences and solving each instance from scratch. Application of ISAT to delay fault testing is presented by formulating incremental path sensitization as an ISAT problem. Non-robust tests for the combinational portion of ISCAS 89 circuits are generated using this method.

On applying incremental satisfiability to delay fault testing

Boolean satisfiability (SAT) and its application to a number of electronic design automation (EDA) problems have been the topic of extensive study over the lost couple of decades. In many cases, a set of related SAT problems need to be solved in order to obtain an answer to a given application-specific problem. Incremental satisfiability (ISAT) refers to solving a set of related SAT problems by augmenting a previously solved problem with additional constraints, thereby reusing previous decision sequences. In this paper, we present a new ISAT engine that supports both the addition and removal of constraints. This can be achieved by keeping track of the relationships between constraints. We identify and define a special type of ISAT that occurs frequently in the context of path sensitization called stack-based ISAT and define the structure of this as a problem tree. In this type of ISAT constraints are allowed to be added and removed only in last-in first-out (LIFO) order. We also introduce a solution caching mechanism to expedite the search by recording and retrieving solutions to intermediate nodes in a problem tree.

On solving stack-based incremental satisfiability problems

Functional delay fault testing is concerned with propagating a transition from a primary input to a primary output of a combinational circuit. Since it does not consider individual paths in the circuit, it can overcome the biggest limitation of path delay fault testing: the explosion in the size of fault lists. Functional delay fault testing can also be used to derive test sets for IP (Intellectual Property) circuits whose implementation details are not provided. Boolean Satisfiability (SAT) and BDDs have been widely used for a variety of EDA (Electronic Design Automation) applications. Even though there have been few experimental studies to conclude the superiority of one to the other, they have been compared for a number of specific tasks in the EDA field. In this paper we show that SAT–based functional delay fault testing can yield very competitive results with careful construction of the CNF formulas for the target faults. In particular, using simple structural analysis of the circuit formulas of minimum size can be easily generated. CNF formula construction based on the circuit consistency function is presented and experimental results for ISCAS 85 and 89 circuits are reported.

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Joonyoung Kim

Papers

SATIRE: a new incremental satisfiability engine

On applying incremental satisfiability to delay fault testing

On solving stack-based incremental satisfiability problems

Satisfiability-Based Functional Delay Fault Testing

Flow Reaction System for the Synthesis of Benzoylacetonitrile Via the Reaction of Amides and Acetonitrile