Showing papers by "José Monteiro published in 1994"

Precomputation-based sequential logic optimization for low power

Abstract: We address the problem of optimizing logic-level sequential circuits for low power We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle We present two different precomputation architectures which exploit this observation The primary optimization step is the synthesis of the precomputation logic, which computes the output values for a subset of input conditions If the output values can be precomputed, the original logic circuit can be "turned off" in the next clock cycle and will have substantially reduced switching activity The size of the precomputation logic determines the power dissipation reduction, area increase and delay increase relative to the original circuit Given a logic-level sequential circuit, we present an automatic method of synthesizing precomputation logic so as to achieve maximal reductions in power dissipation We present experimental results on various sequential circuits Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay >

A Methodology for Efficient Estimation of Switching Activity in Sequential Logic Circuits

Abstract: We describe a computationally efficient scheme to approximate average switching activity in sequential circuits which requires the solution of a non-linear system of equations of size N, where the variables correspond to state line probabilities. We show that the approximation method is within 3% of the exact Chapman-Kolmogorov method, but is orders of magnitude faster for large circuits. Previous sequential switching activity estimation methods can have significantly greater inaccuracies.

Precomputation-based sequential logic optimization for low power

Abstract: We address the problem of optimizing logic-level sequential circuits for low power We present a powerful sequential logic optimization method that is based on selectively precomputing the output logic values of the circuit one clock cycle before they are required, and using the precomputed values to reduce internal switching activity in the succeeding clock cycle We present two different precomputation architectures which exploit this observationWe present an automatic method of synthesizing precomputational logic so as to achieve maximal reductions in power dissipation We present experimental results on various sequential circuits Up to 75% reductions in average switching activity and power dissipation are possible with marginal increases in circuit area and delay

Bitwise encoding of finite state machines

Abstract: We propose an innovative method of encoding the states of finite state machines. Our approach consists of iteratively defining the code word, one bit at a time. In each iteration the input state machine is decomposed into two submachines, with the first submachine having only two states. One bit is therefore sufficient to encode this submachine and it can be assigned arbitrarily as the particular value it assumes for each state is of minimal influence in terms of the machine implementation. The process is repeated again having as input the second submachine, until all the bits are encoded. We provide experimental results which indicate that our method of iteratively defining one bit at a time can generally achieve superior results to existing sequential state assignment methods which try to solve large problems heuristically. >