Showing papers by "José Monteiro published in 2001"

Power Efficient Arithmetic Operand Encoding

Abstract: This paper addresses the use of alternative codes for arithmetic operators. The objective is twofold. First, to investigate operand codes that yield simpler, i.e., power efficient, arithmetic modules. Second, to investigate signal encodings that lead to the reduction of the switching activity in the data buses. Although signal correlation is more relevant for address buses, where signal encoding has received much attention, in many cases correlation in the data buses is still very significant. By using low-switching operand codes directly in the arithmetic modules, the process of encoding and decoding of the signals can be avoided. We propose a Hybrid encoding for the operators, which is a compromise between the minimal input dependency presented by the Binary encoding and the low switching characteristic of the Gray encoding. We present a methodology for the generation of arithmetic operators, such as adders and multipliers, using Hybrid encoded operands. The overall area, delay and power consumption under different word size operators are evaluated for both the Hybrid and Binary modules. The results show that power savings of up to 30% in array multiplier modules are possible, with 33% reduction in the switched capacitance in the buses. Additionally, a 17% delay improvement is achieved, with an area penalty of 30%. The Hybrid encoding can also be as easily used in address buses where the same 33% savings can be obtained with low overhead transcoders.

Power efficient arithmetic operand encoding [CMOS circuits]

Abstract: Addresses the use of alternative codes for arithmetic operators. The objective is twofold. First, to investigate operand codes that yield simpler, i.e., power efficient, arithmetic modules. Second, to investigate signal encodings that lead to the reduction of the switching activity in the data buses. Although signal correlation is more relevant for address buses, where signal encoding has received much attention, in many cases correlation in the data buses is still very significant. By using low-switching operand codes directly in the arithmetic modules, the process of encoding and decoding of the signals can be avoided. We propose a hybrid encoding for the operators, which is a compromise between the minimal input dependency presented by binary encoding and the low switching characteristic of Gray encoding. We present a methodology for the generation of arithmetic operators, such as adders and multipliers, using hybrid encoded operands. The overall area, delay and power consumption under different word size operators are evaluated for both the hybrid and binary modules. The results show that power savings of up to 30% in array multiplier modules are possible, with 33% reduction in the switched capacitance in the buses. Additionally, a 17% delay improvement is achieved, with an area penalty of 30%. The hybrid encoding can also be as easily used in address buses where the same 33% savings can be obtained with low overhead transcoders.

Power Optimized Viterbi Decoder Implementation through Architectural Transforms

Abstract: Viterbi is an algorithm for error correction in the transmission of messages. It requires coding and decoding stages in the sender and receiver, respectively. These type of algorithms are very useful for the transmission of a type of messages where some degree of error in the received message is acceptable, such as, voice and video. The coding allows some error detection and correction. In this paper we present an architecture for the Viterbi Decoder. Using this initial structure, we have applied a set of transformation techniques aiming for a power optimized implementation. These techniques include pipelining, operation reduction/substitution and the reduction of transition activity. We show that it is possible to reduce the circuit's power consumption by more than half without impacting excessively on the area.