In this paper, the optimization issues of various drain-extended devices are discussed for input/output applications. The mixed-signal performance, impact of process variations, and gate oxide reliability of these devices are compared. Lightly doped drain MOS (LDDMOS) was found to have a moderate performance advantage as compared to shallow trench isolation (STI) and non-STI drain-extended MOS (DeMOS) devices. Non-STI DeMOS devices have improved circuit performance but suffer from the worst gate oxide reliability. Incorporating an STI region underneath the gate-drain overlap improves the gate oxide reliability, although it degrades the mixed-signal characteristics of the device. The single-halo nature of DeMOS devices has been shown to be effective in suppressing the short-channel effects.

Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices

In this work a new probabilistic and dynamical approach to an extension of the Gompertz law is proposed. A generalized family of probability density functions, designated by $Beta^*(p,q)$, which is proportional to the right hand side of the Tsoularis-Wallace model, is studied. In particular, for $p = 2$, the investigation is extended to the extreme value models of Weibull and Frechet type. These models, described by differential equations, are proportional to the hyper-Gompertz growth model. It is proved that the $Beta^*(2,q)$ densities are a power of betas mixture, and that its dynamics are determined by a non-linear coupling of probabilities. The dynamical analysis is performed using techniques of symbolic dynamics and the system complexity is measured using topological entropy. Generally, the natural history of a malignant tumour is reflected through bifurcation diagrams, in which are identified regions of regression, stability, bifurcation, chaos and terminus.

An extension of Gompertzian growth dynamics: Weibull and Frechet models

In this paper, high-voltage (HV)-tolerant level shifters with combinational functionality are proposed based on differential cascode voltage switch logic (DCVSL). These level shifters are tolerant to supply voltages higher than the process limit for individual CMOS transistors. The proposed HV DCVSL level shifters are particularly useful when it is mandatory to constrain the output using a logic function during out of the normal mode periods (power-up, power-down, reset, etc.). These HV-tolerant logic circuits were used in the power block of a buck converter designed in a standard 3.3-V 0.13-mum CMOS process, powered by an input voltage range from 2.7 to 4.2 V. Simulation and experimental results of the buck are analyzed, and the topology is evaluated.

/pdf/level-shifters-and-dcvsl-for-a-low-voltage-cmos-4-2-v-buck-43mo953ck8.pdf

Level Shifters and DCVSL for a Low-Voltage CMOS 4.2-V Buck Converter

This paper concerns dynamics and bifurcations properties of a class of continuous-defined one-dimensional maps, in a three-dimensional parameter space: Blumberg’s functions. This family of functions naturally incorporates a major focus of ecological research: the Allee effect. We provide a necessary condition for the occurrence of this phenomenon, associated with the stability of a fixed point. A central point of our investigation is the study of bifurcations structure for this class of functions. We verified that under some sufficient conditions, Blumberg’s functions have a particular bifurcations structure: the big bang bifurcations of the so-called “box-within-a-box” type, but for different kinds of boxes. Moreover, it is verified that these bifurcation cascades converge to different big bang bifurcation curves, where for the corresponding parameter values are associated distinct attractors. This work contributes to clarify the big bang bifurcation analysis for continuous maps. To support our results, we present fold and flip bifurcations curves and surfaces, and numerical simulations of several bifurcation diagrams.

Big bang bifurcations and Allee effect in Blumberg’s dynamics

In this paper we define and investigate generalized Richards' growth models with strong and weak Allee effects and no Allee effect. We prove the transition from strong Allee effect to no Allee effect, passing through the weak Allee effect, depending on the implicit conditions, which involve the several parameters considered in the models. New classes of functions describing the existence or not of Allee effect are introduced, a new dynamical approach to Richards' populational growth equation is established. These families of generalized Richards' functions are proportional to the right hand side of the generalized Richards' growth models proposed. Subclasses of strong and weak Allee functions and functions with no Allee effect are characterized. The study of their bifurcation structure is presented in detail, this analysis is done based on the configurations of bifurcation curves and symbolic dynamics techniques. Generically, the dynamics of these functions are classified in the following types: extinction, semi-stability, stability, period doubling, chaos, chaotic semistability and essential extinction. We obtain conditions on the parameter plane for the existence of a weak Allee effect region related to the appearance of cusp points. To support our results, we present fold and flip bifurcations curves and numerical simulations of several bifurcation diagrams.

/pdf/strong-and-weak-allee-effects-and-chaotic-dynamics-in-2lpq1nwt33.pdf

Strong and weak Allee effects and chaotic dynamics in Richards' growths

In this paper, high voltage (HV) tolerant level-shifters with combinational functionality are proposed based on differential cascode voltage switch logic (DCVSL). These level-shifters are tolerant to supply voltages higher than the process limit for individual CMOS transistors. The proposed HV DCVSL level shifters are particularly useful when it is mandatory to ensure a specific behavior during out of the normal mode periods (power up; power down; reset; etc.). These high voltage tolerant logic circuits were used in the power block of buck converter designed in a standard 3.3 V, 0.13 mum CMOS process, powered by an input voltage range from 2.7 V to 4.2 V.

High Voltage Tolerant Level Shifters and DCVSL in Standard Low Voltage CMOS Technologies

We present a new dynamical approach to the Blumberg's equation, a family of unimodal maps. These maps are proportional to $Beta(p,q)$ probability densities functions. Using the symmetry of the $Beta(p,q)$ distribution and symbolic dynamics techniques, a new concept of mirror symmetry is defined for this family of maps. The kneading theory is used to analyze the effect of such symmetry in the presented models. The main result proves that two mirror symmetric unimodal maps have the same topological entropy. Different population dynamics regimes are identified, when the intrinsic growth rate is modified: extinctions, stabilities, bifurcations, chaos and Allee effect. To illustrate our results, we present a numerical analysis, where are demonstrated: monotonicity of the topological entropy with the variation of the intrinsic growth rate, existence of isentropic sets in the parameters space and mirror symmetry.

/pdf/dynamical-analysis-in-growth-models-blumberg-s-equation-obo406ktf8.pdf

Dynamical analysis in growth models: Blumberg’s equation

In this work we establish new one-dimensional discrete dynamical systems: a family of unimodal maps that is proportional to the right hand side of Richards’ growth equation. We investigate in detail the bifurcation structure of Richards’ functions, on the twodimensional parameter space (β,r), where β is the shape parameter, related with the growth-retardation phenomena, and r is the intrinsic growth rate. Sufficient conditions are provided for the occurrence of extinction, stability, period doubling, chaos and non admissibility of Richards’ dynamics. We consider networks having in each node a Richards’ function. We prove some results about the synchronization level when fixing the network topology and changing the local dynamics expressed by the Lyapunov exponents, which depends on the (β,r) parameters. Moreover, we fix the local dynamics and prove results about the synchronization when the network topology change for some kind of networks. Finally, using numerical simulations, we compute the Lyapunov exponents to measure the system complexity, we obtain synchronization intervals of these networks, and we discuss the evolution of the synchronization level in terms of the parameters Richard’s function.

Synchronization in Richards’ Chaotic Systems

Implementing monolithic DC-DC converters for low power portable applications with a standard low voltage CMOS technology leads to lower production costs and higher reliability. Moreover, it allows miniaturization by the integration of two units in the same die: the power management unit that regulates the supply voltage for the second unit, a dedicated signal processor, that performs the functions required. This paper presents original techniques that limit spikes in the internal supply voltage on a monolithic DC-DC converter, extending the use of the same technology for both units. These spikes are mainly caused by fast current variations in the path connecting the external power supply to the internal pads of the converter power block. This path includes two parasitic inductances inbuilt in bond wires and in package pins. Although these parasitic inductances present relative low values when compared with the typical external inductances of DC-DC converters, their effects can not be neglected when switching high currents at high switching frequency. The associated overvoltage frequently causes destruction, reliability problems and/or control malfunction. Different spike reduction techniques are presented and compared. The proposed techniques were used in the design of the gate driver of a DC-DC converter included in a power management unit implemented in a standard 0.35µm CMOS technology.

https://repositorio.ipl.pt/bitstream/10400.21/696/1/Limiting%20Internal%20Supply%20Voltage%20Spikes%20in%20DC-DC%20Converters_rep.pdf

Limiting internal supply voltage spikes in DC-DC converters

One of the ultimate goals of researches on complex networks is to understand how the structure of complex networks affects the dynamical process taking place on them, such as traffic flow, epidemic spread, cascading behavior, and so on. In previous works [1] and [2], we have studied the synchronizability of a network in terms of the local dynamics, supposing that the topology of the graph is fixed. Now, we are interested in studying the effects of the structure of the network, i.e., the topology of the graph on the network synchronizability. The synchronization interval is given by a formula relating the first non zero and the largest eigenvalue of the Laplacian matrix of the graph with the maximum Lyapunov exponent of the local nodes. Our goal is to understand under what conditions can ensure the formation of clusters depending on the conductance and the coefficient of clustering

http://www.researchgate.net/profile/Acilina_Caneco/publication/232166520_Conditions_for_the_formation_of_clusters_depending_on_the_conductance_and_the_coefficient_of_clustering/links/0912f507c31ed4859c000000.pdf

Jose Rocha

Papers

High Voltage Tolerant Level Shifters and DCVSL in Standard Low Voltage CMOS Technologies

Dynamical analysis in growth models: Blumberg’s equation

Synchronization in Richards’ Chaotic Systems

Limiting internal supply voltage spikes in DC-DC converters

Conditions for the formation of clusters depending on the conductance and the coefficient of clustering