Proceedings ArticleDOI
High Voltage Tolerant Level Shifters and DCVSL in Standard Low Voltage CMOS Technologies
Jose Rocha,M. B. Santos,José M. Dores Costa,F. Lima +3 more
- pp 775-780
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TLDR
In this article, high voltage tolerant level shifters with combinational functionality are proposed based on differential cascode voltage switch logic (DCVSL), which are tolerant to supply voltages higher than the process limit for individual CMOS transistors.Abstract:
In this paper, high voltage (HV) tolerant level-shifters with combinational functionality are proposed based on differential cascode voltage switch logic (DCVSL). These level-shifters are tolerant to supply voltages higher than the process limit for individual CMOS transistors. The proposed HV DCVSL level shifters are particularly useful when it is mandatory to ensure a specific behavior during out of the normal mode periods (power up; power down; reset; etc.). These high voltage tolerant logic circuits were used in the power block of buck converter designed in a standard 3.3 V, 0.13 mum CMOS process, powered by an input voltage range from 2.7 V to 4.2 V.read more
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Journal ArticleDOI
Part I: Mixed-Signal Performance of Various High-Voltage Drain-Extended MOS Devices
TL;DR: In this paper, the optimization issues of various drain-extended devices are discussed for input/output applications, including mixed-signal performance, impact of process variations, and gate oxide reliability.
Journal ArticleDOI
Level Shifters and DCVSL for a Low-Voltage CMOS 4.2-V Buck Converter
TL;DR: In this paper, high-voltage (HV)-tolerant level shifters with combinational functionality are proposed based on differential cascode voltage switch logic (DCVSL), tolerant to supply voltages higher than the process limit for individual CMOS transistors.
Patent
Capacitive level shifter devices, methods and systems
TL;DR: In this article, the authors describe a circuit that is designed to detect the state of two control signals, where one control signal indicates an ON state for the gate driver and the other one indicates an OFF state for a gate driver.
Patent
Capacitive isolated voltage domains
TL;DR: In this paper, a receiver circuit is configured to receive a modulated signal from a transmitter that is galvanically isolated from the receiver circuit, and the receiver circuits are configured to demodulate the modulated signals by using two comparator circuits that respectively detect the presence or absence of first and second signal states of a carrier signal.
Patent
Bond wire arrangement for efficient signal transmission
TL;DR: In this article, the authors propose a device that includes a first IC having a differential signal driver and a first isolation circuit configured to provide differential signals transmitted by the differential signal drivers to a first pair of bond pads of the first IC.
References
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Proceedings ArticleDOI
Cascode voltage switch logic: A differential CMOS logic family
TL;DR: A differential CMOS Logic family that is well suited to automated logic minimization and placement and routing techniques, yet has comparable performance to conventional CMOS, will be described.
Journal ArticleDOI
A comparison of CMOS circuit techniques: differential cascode voltage switch logic versus conventional logic
K.M. Chu,D.L. Pulfrey +1 more
TL;DR: A detailed comparison of DCVS logic and conventional logic is carried out by simulation, using SPICE, of the performance of full adders designed using the different circuit techniques.
Journal ArticleDOI
A versatile 3.3 V/2.5 V/1.8 V CMOS I/O driver built in a 0.2 /spl mu/m 3.5 nm Tox 1.8 V CMOS technology
TL;DR: The continued scaling of transistor performance is delivering unprecedented microprocessor performance, however, the logic supply voltage, Vdd, is being reduced at a faster rate than the required I/O voltage level, OVDD, which scales more slowly due to peripherals.
Journal ArticleDOI
A high-voltage output driver in a 2.5-V 0.25-/spl mu/m CMOS technology
TL;DR: In this article, a high-voltage output driver in a digital 0.25-/spl mu/m 2.5-V technology is presented, which uses stacked devices with a self-biased cascode topology, allowing the driver to operate at three times the nominal supply voltage.
Proceedings ArticleDOI
A low voltage to high voltage level shifter circuit for MEMS application
TL;DR: In this article, a low voltage to high voltage converter circuit was proposed to solve the high voltage swing problem in a 0.35 SOI process, where all the low voltage devices were removed.