Showing papers by "Juergen Becker published in 2010"

KAHRISMA: a novel hypermorphic reconfigurable-instruction-set multi-grained-array architecture

Abstract: Facing the requirements of next generation applications, current approaches of embedded systems design will soon hit the limit where they may no longer perform efficiently. The unpredictable nature and diverse processing behavior of future applications requires to transgress the barrier of tailor-made, application-/domain-specific embedded system designs. As a consequence, next generation architectures for embedded systems have to react much more flexible to unforeseeable run-time scenarios. In this paper we present our innovative processor architecture concept KAHRISMA (KArlsruhe's Hypermorphic Reconfigurable-Instruction-Set Multi-grained-Array). It tightly integrates coarse- and fine-grained run-time reconfigurable fabrics that can incorporate to realize hardware acceleration for computationally complex algorithms. Furthermore, the fabrics can be combined to realize different Instruction Set Architectures that may execute in parallel. With the help of an encrypted H.264 en-/decoding case study we demonstrate that our novel KAHRISMA architecture will deliver the required flexibility to design future-proof embedded systems that are not limited to a certain computational domain.

Reliability Analysis and Improvement in Nano Scale Design

Abstract: According to the shrinking feature size of the VLSI circuits it is expected that nano scale devices and interconnections will introduce unprecedented level of defects and architectural designs need to settle with the uncertainty result at such scales. Several approaches for implementing the fault tolerance systems are already investigated. Most of these methods are applicable also in the case of high fault rates. Most protection methods are based on different redundancy methods which add extra detection and correction features to the design. We strongly believe that in future architectures it become more important assessing the fault tolerance techniques. Having an estimation of system fault tolerance can ensure critical applications working properly. In this work we propose a new method which checks reconfigurable architectures and during runtime finds violent spots in the design for probable transient and permanent failures. This approach is adjustable to either current FPGAs or future nano-architectures which are based on reconfigurability. We define a fault detection model for probable errors which uses an efficient algorithm that proves the fault tolerance in the reconfigurable architecture and computes a reliability factor for the architecture. This helps avoiding using the critical parts by future usages. Our method is applicable to different levels of granularity, such as gate level, logic block level, logic function level, unit level, etc. It is efficient and fast and can be simply integrated into the design flow.

A semi-automatic toolchain for reconfigurable multiprocessor systems-on-chip: architecture development and application partitioning (abstract only)

Abstract: The efficient automatized application partitioning and mapping process for multiprocessor systems is a challenging task in academics as well as in industry until today The introduction of reconfigurable hardware in this domain helps to meet the application requirements more efficiently due to the method of hardware adaptation at design and runtime The combination of multiprocessor systems-on-chip (MPSoC) and reconfigurable hardware results in the RAMPSoC approach (Runtime Adaptive MPSoC) A RAMPSoC consists of an adaptive network of processors and hardware accelerators This novel degree of freedom in MPSoC technology and the resulting design space has to be processed by a suitable toolchain, which helps to hide the complexity of the hardware architecture and its realization alternatives from the developer This work investigates in an approach for a semi-automatic toolchain for the development of the hardware architecture and the application partitioning and mapping A multistep approach is used to analyze and partition the software application First each function of the software application is profiled and the communication overhead between the functions is analyzed The results, obtained from the profiling and the communication analysis, are used as parameters for the cost function of a hierarchical clustering algorithm The functions are clustered into multiple application modules for a given number of processors In a second step, for each processor the corresponding application module is analyzed concerning computation intensive blocks or loops Out of this results a Hardware/Software Co-design partitioning with a suggestion for possible hardware accelerators for each of the processors This allows to achieve a performance near to the maximum of the local processors and therefore in general for the MPSoC The third and last step in the designflow handles the generation of the bitstream for the complete system together with the software executables for each of the processors This semi-automatic toolchain has been evaluated using an image processing algorithm

Energy-Autarkic Monitor for FTTx Networks

Abstract: FTTx monitors with sophisticated hardware need 0.7µW of electrical power when controlled through a special protocol. This power can be delivered by a 5dBm optical source at a dedicated wavelength to up to 64 monitors.