Reliability concerns due to technology scaling have been a major focus of researchers and designers for several technology nodes. Therefore, many new techniques for enhancing and optimizing reliability have emerged particularly within the last five to ten years. This perspective paper introduces the most prominent reliability concerns from today's points of view and roughly recapitulates the progress in the community so far. The focus of this paper is on perspective trends from the industrial as well as academic points of view that suggest a way for coping with reliability challenges in upcoming technology nodes.

Reliable on-chip systems in the nano-era: lessons learnt and future trends

Today, soft errors are one of the major design technology challenges at and beyond the 22nm technology nodes. This article introduces the soft error problem from the perspective of processor design. This article also provides a survey of the existing soft error mitigation methods across different levels of design abstraction involved in processor design, including the device level, the circuit level, the architectural level, and the program level.

Processor Design for Soft Errors: Challenges and State of the Art

We present a first of its kind framework which overcomes a major challenge in the design of digital systems that are resilient to reliability failures: achieve desired resilience targets at minimal costs (energy, power, execution time, area) by combining resilience techniques across various layers of the system stack (circuit, logic, architecture, software, algorithm). This is also referred to as cross-layer resilience. In this paper, we focus on radiation-induced soft errors in processor cores. We address both single-event upsets (SEUs) and single-event multiple upsets (SEMUs) in terrestrial environments. Our framework automatically and systematically explores the large space of comprehensive resilience techniques and their combinations across various layers of the system stack (798 cross-layer combinations in this paper), derives cost-effective solutions that achieve resilience targets at minimal costs, and provides guidelines for the design of new resilience techniques. We demonstrate the practicality and effectiveness of our framework using two diverse designs: a simple, in-order processor core and a complex, out-of-order processor core. Our results demonstrate that a carefully optimized combination of circuit-level hardening, logic-level parity checking, and micro-architectural recovery provides a highly cost-effective soft error resilience solution for general-purpose processor cores. For example, a 50∗ improvement in silent data corruption rate is achieved at only 2.1% energy cost for an out-of-order core (6.1% for an in-order core) with no speed impact. However, selective circuit-level hardening alone, guided by a thorough analysis of the effects of soft errors on application benchmarks, provides a cost-effective soft error resilience solution as well (with ∼1% additional energy cost for a 50∗ improvement in silent data corruption rate).

CLEAR: C ross -L ayer E xploration for A rchitecting R esilience - Combining hardware and software techniques to tolerate soft errors in processor cores

Today's mainstream electronic systems typically assume that transistors and interconnects operate correctly over their useful lifetime. With enormous complexity and significantly increased vulnerability to failures compared to the past, future system designs cannot rely on such assumptions. For coming generations of silicon technologies, several causes of hardware reliability failures, largely benign in the past, are becoming significant at the system level. Robust system design is essential to ensure that future systems perform correctly despite rising complexity and increasing disturbances. This paper describes three techniques that can enable a sea change in robust system design through cost-effective tolerance and prediction of failures in hardware during system operation: 1) efficient soft error resilience; 2) circuit failure prediction; and 3) effective on-line self-test and diagnostics. The need for global optimization across multiple abstraction layers is also demonstrated.

Robust System Design to Overcome CMOS Reliability Challenges

A layout structure to avoid upsets due to Multiple Cell Upsets (MCUs) is proposed for rad-hard dual-modular Flip-Flops (FFs) called BCDMR (Bistable Cross-coupled Dual-Modular Redundancy) by separating critical components. We have fabricated a 65 nm chip including 30 kbit dual-modular FF arrays on twin-well and triple-well structures. High-energy broad-spectrum neutron irradiations reveal that no soft error is observed up to 100 MHz in the twin-well, but some errors are observed in the triple well. The triple-well structure is sensitive to MCUs because the p-well potential can be easily elevated.

/pdf/an-area-efficient-65-nm-radiation-hard-dual-modular-flip-3vdqcdokbz.pdf

An Area-Efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets

In this paper, we propose a low-power area-efficient redundant flip-flops for soft errors, called DICE-ACFF. Its structure is based on the reliable DICE (Dual Interlocked storage CEll) and the low-power ACFF (Adaptive-Coupling Flip-Flop). It achieves lower power at lower data-activity. We designed DICE-FF and DICE-ACFF using 65 nm conventional bulk and thin-BOX FD-SOI (Silicon on Thin-BOX, SOTB) processes. Its area is twice as large as the conventional DFF. As for power dissipation, DICE ACFF achieves lower power than the conventional DFF below 20% data activity. When data activity is 0%, its power is half of the DFF. As for soft error rates DICE ACFFs are 1.5x stronger than conventional DICE FFs by circuit-level simulations to estimate critical charge. No SEU is observed on the DICE ACFF by alpha-particle irradiation at 1.2V on the bulk and and SOTB chips. The soft error rates of the DFF of the SOTB chip is 1/200 compared with that of the bulk chip.

A low-power and area-efficient radiation-hard redundant flip-flop, DICE ACFF, in a 65 nm thin-BOX FD-SOI

We propose a Bistable Cross-coupled Dual Modular Redundancy (BCDMR) Flip-Flop to enhance soft-error immunity. It is based on a BISER FF but its bistable cross-coupled structure enhances soft-error immunity without any area, delay and power overhead. We fabricated a 65nm LSI including 60,480bit shift registers with the BCDMR and BISER structures. Experimental results using α-particles reveals that the soft-error immunity of the BCDMR is enhanced by 150x at 160MHz clock frequency compared with the BISER.

/pdf/a-65nm-bistable-cross-coupled-dual-modular-redundancy-flip-5fxz399v9g.pdf

A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop capable of protecting soft errors on the C-element

In this paper, we propose radiation-hardened flip-flops (FFs) based on the adaptive coupling FF with low dynamic power and short delay overhead in a 65-nm fully depleted silicon on insulator process. We designed four FFs composed of a master latch with pMOS pass-transistors to reduce a delay time overhead and a slave latch with stacked transistors for high soft-error tolerance. We evaluated the radiation hardness of the newly designed FFs using TCAD simulations, $\alpha$ particle test, and neutron irradiation test. TCAD simulations show that the proposed structure has enough radiation hardness against secondary particles generated by neutrons. The $\alpha$ irradiation results show that error probabilities of the proposed FFs are 1/400–1/130 smaller than conventional radiation-hardened stacked FF. Neutron irradiation results show that soft-error rates of the proposed FFs are 1/16–1/7 lower than stacked FF. No significant differences in soft-error tolerance were observed in any of the proposed FFs under all static conditions. The experimental results suggest that the pMOS pass-transistors can effectively suppress soft errors in terrestrial regions with a low-delay overhead.

Radiation-Hardened Flip-Flops With Low-Delay Overhead Using pMOS Pass-Transistors to Suppress SET Pulses in a 65-nm FDSOI Process

We measured neutron-induced Single Event Upsets (SEUs) and Multiple Cell Upsets (MCUs) on Flip-Flops (FFs) in a 65 nm bulk CMOS process. Measurement results show that MCU / SEU is up to 23.4% and is exponentially decreased by the distance between latches on FFs. MCU rates can drastically be reduced by inserting well-contact arrays between FFs. The number of MCUs is reduced from 110 to 1 by inserting a well-contact array under power and ground rails.

/pdf/impact-of-cell-distance-and-well-contact-density-on-neutron-2f970qd772.pdf

Jun Furuta

Papers

An Area-Efficient 65 nm Radiation-Hard Dual-Modular Flip-Flop to Avoid Multiple Cell Upsets

A low-power and area-efficient radiation-hard redundant flip-flop, DICE ACFF, in a 65 nm thin-BOX FD-SOI

A 65nm Bistable Cross-coupled Dual Modular Redundancy Flip-Flop capable of protecting soft errors on the C-element

Radiation-Hardened Flip-Flops With Low-Delay Overhead Using pMOS Pass-Transistors to Suppress SET Pulses in a 65-nm FDSOI Process

Impact of cell distance and well-contact density on neutron-induced Multiple Cell Upsets