Showing papers by "Jun Suda published in 2004"

4h-polytype gallium nitride-based semiconductor device on a 4h-polytype substrate

Abstract: 4H—InGaAlN alloy based optoelectronic and electronic devices on non-polar face are formed on 4H—AlN or 4H—AlGaN on (11-20) a-face 4H—SiC substrates. Typically, non polar 4H—AlN is grown on 4H—SiC (11-20) by molecular beam epitaxy (MBE). Subsequently, III-V nitride device layers are grown by metal organic chemical vapor deposition (MOCVD) with 4H-polytype for all of the layers. The non-polar device does not contain any built-in electric field due to the spontaneous and piezoelectric polarization. The optoelectronic devices on the non-polar face exhibits higher emission efficiency with shorter emission wavelength because the electrons and holes are not spatially separated in the quantum well. Vertical device configuration for lasers and light emitting diodes (LEDs) using conductive 4H—AlGaN interlayer on conductive 4H—SiC substrates makes the chip size and series resistance smaller. The elimination of such electric field also improves the performance of high speed and high power transistors. The details of the epitaxial growth s and the processing procedures for the non-polar III-V nitride devices on the non-polar SiC substrates are also disclosed.

High Channel Mobilities of MOSFETs on Highly-Doped 4H-SiC (11-20) Face by Oxidation in N2O Ambient

Abstract: Planar n-channel MOSFETs have been fabricated on 4H-SiC (11-20), (0001) and (000-1) faces by using oxidation in N2O ambient. The relationship between the MOSFET performance and the acceptor concentration (7×10 15 -2×10 17 cm -3 ) of epilayers has been investigated. 4H-SiC (11-20) MOSFETs have shown a high effective channel mobility of 70 cm 2 /Vs at a 2×10 16 cm -3 doping, and 54 cm 2 /Vs at 2×10 17 cm -3 . Short-channel effects have been also investigated.

Towards High-Quality AlN/SiC Hetero-Interface by Controlling Initial Processes in Molecular-Beam Epitaxy

Abstract: The electronic properties of AlN/SiC hetero-interface were investigated by using Al/AlN/4H-SiC MIS capacitors. Single crystalline AlN was grown on n-type 8° off-axis 4H-SiC (0001) epilayers via plasma-assisted molecular-beam epitaxy (PA-MBE). The C-V characteristics revealed that the initial pre-irradiation of atomic nitrogen (N*) before AlN growth strongly affected the electronic properties of AlN/SiC interface, which probably attributed to the atomic arrangement of Al, N, Si and C at the interface. A noticeably small value of interface state density (Dit), such as 3×10 cm·eV at Ec-0.2 eV, was obtained for the N* pre-irradiated interface. Introduction Aluminum nitride (AlN) is a group-III nitride material with a wurtzite structure. The in-plane lattice mismatch between AlN and hexagonal silicon carbide (SiC) is as small as 0.9%, and their thermal expansion coefficients are almost same [1]. Because of the good matching, single crystalline AlN can be grown on SiC (0001). The large bandgap of AlN (6.2 eV) makes it an attractive insulator for SiC metal-insulator-semiconductor (MIS) devices. We have successfully grown highly-insulating AlN on 6H-SiC (0001) on-axis substrates by SiC surface control in plasma-assisted molecular-beam epitaxy (PA-MBE) [2,3]. To utilize AlN for SiC MIS devices, there are two important things: (1) AlN should be grown on an SiC (0001) epilayer with an off angle; (2) Besides insulating properties, control of electronic properties in the AlN/SiC interface (density of interface traps, channel mobility etc.) is essential. Although an AlN/SiC heterostructure is expected to be a promising alternative to a SiO2/SiC MOS structure, the interface characteristics have not been understood in detail. Conditions of AlN/SiC interface formation, e.g. initial sequence in AlN growth or AlN layer thickness, are thought to strongly influence on the electronic properties. In this study we investigate the electronic properties of AlN/SiC interface by using Al/AlN/4H-SiC MIS capacitors, and the influence of AlN growth conditions on the interface characteristics, such as interface states and flat-band shift, is discussed. Experimental details AlN was grown via PA-MBE on 8-μm-thick n-type 8° off-axis 4H-SiC (0001) epilayers. The doping level of epilayer was about 1×10 cm. The substrates were first degreased using conventional organic solvents, and then dipped in HCl, HCl+HNO3 (3:1) and HF solutions. After the wet chemical process, they were loaded into an MBE system. The MBE chamber is equipped with effusion cells for elemental Ga and Al evaporation and an EPI Unibulb radio-frequency (rf) plasma cell for producing active nitrogen (N*). In the MBE chamber, Ga metal was deposited on the substrates at 600°C, and then the substrate temperature was raised to 1000°C to desorb the deposited Ga metal. This procedure was intended to remove residual oxygen from the SiC surface [4]. AlN growth was carried out at 600°C and 1000°C. For some samples, AlN growth was initiated with N* pre-irradiation for 1 min to examine the influence on the electronic properties of AlN/SiC interface. The total thickness of Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 1569-1572 doi:10.4028/www.scientific.net/MSF.457-460.1569 © 2004 Trans Tech Publications Ltd, Switzerland All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications Ltd, www.scientific.net. (Semanticscholar.org-11/03/20,15:23:19) 2 Title of Publication (to be inserted by the publisher) epilayer ranged from 10 to 200 nm. Al electrodes (150 μm in diameter) were deposited on AlN surfaces by vacuum evaporation for current-voltage (I-V) and capacitance-voltage (C-V) measurements. Results and discussion Figures 1(a) and 1(b) show the AFM micrographs of AlN epilayers grown at 600°C and 1000°C, respectively. The AlN epilayer grown at 600°C exhibited an atomically smooth surface with a root-mean-square (rms) roughness of 0.3 nm. Atomic steps with 1-2 monolayer (ML)-height were evidently observed toward the [11-20] off-direction. On the other hand, the 1000°C-grown AlN epilayer had surface undulation, and the rms roughness was large, such as 1.3 nm. From the viewpoint of surface smoothness, the 600°C-grown AlN epilayer is preferable. As to the crystalline quality of those AlN epilayers investigated by high-resolution x-ray diffraction (HRXRD), there was no large difference between 600°Cand 1000°C-grown AlN epilayers. Both epilayers were found to have sufficient quality for applying to MIS devices. The insulating properties of 70-nm-thick AlN epilayer were examined by I-V measurement. The bias direction was an accumulation mode, i.e., the Al electrode was biased to positive. The insulating properties shown in Fig. 2 are satisfactory for applying to MIS devices. The resistivity in a low electric field was about 10 Ω·cm and the breakdown field was over 3.8 MV/cm. The influence of initial growth sequence on the electronic properties of AlN/SiC interface was investigated. Figure 3 shows the results of high-frequency (1MHz) C-V measurements without initial N* pre-irradiation, in other words, AlN growth was initiated with Al and N* irradiation at the same time. All samples exhibited a positive flat-band shift, indicating negative charges at the interface. This result applies to both 600°Cand 1000°C-grown AlN epilayers. <1120> 200 nm rms roughness 0.3 nm <1120> 200 nm rms roughness 1.3 nm 5 nm

Influence of Substrate Misorientation Angle and Direction in Growth of GaN on Off-axis SiC (0001)

Abstract: Growth of GaN on 4H- or 6H-SiC (0001) Si-face substrates with various misorientation angles and directions is presented. GaN layers were directly grown on the SiC substrates by molecular-beam epitaxy using elemental Ga and rf plasma-excited active nitrogen. First, 4H-SiC (0001) 8°-off toward the [11-20] direction was investigated. Before the growth of GaN, ex-situ high-temperature gas etching was carried out, resulting in a smooth SiC initial surface. However, the surface of the subsequently grown GaN layer has wavy features with peak-to-valley height of 30 nm. Since the direction of the undulations is parallel to the misorientation direction, this feature must originate from the substrate misorientation. Step bunching and large faceting along and directions occurred during the growth of GaN. Lowering the growth temperature suppresses large faceting, and results in reduction of the peak-to-valley height to 3 nm. However, the surface still has the same undulating features on a smaller length scale. On the other hand such morphology was not observed for GaN grown on (0001) on-axis SiC substrates (misorientation < 0.3°). The influence of the polytype of the SiC substrate and the misorientation angle and direction are also discussed.

4H-SiC MOSFETs with a Novel Channel Structure (Sandwiched Channel MOSFET)

Abstract: 4H-SiC MOSFETs with a novel channel structure are presented. In the novel MOSFETs, a buried n-channel is sandwiched by a thin p-layer and p-body (SC-MOSFET). By the introduction of properly-designed p-layer beneath the gate oxide, more electrons can travel apart from the MOS interface, leading to higher channel mobility especially at high gate voltage. In this study, the effects of channel structure on the 4H-SiC (0001) MOSFET performance are investigated, and the characteristics of inversion-type MOSFET, ACCUFET and SC-MOSFET were compared. The SC-MOSFET, processed by N2O oxidation, with a 0.10 μm-thick channel showed a high mobility of 40 cm 2 /Vs with a normally-off characteristic at 2.5 MV/cm. Introduction SiC MOSFETs are expected to show high switching speed, low energy loss, and the capability of high-temperature operation. However, the performance of fabricated SiC power MOSFETs is far from the expected level, due to the large channel resistance especially for 4H-SiC (0001) MOSFETs. It is considered that high density traps at the SiO2/SiC interface degrade the channel mobility [1, 2]. Although a very high mobility of 140-240 cm 2 /Vs has been reported for ACCUFETs (ACCumulation -mode MOSFET) or buried channel MOSFETs [3, 4], the peak mobility is not always a good figure when discussing the on-resistance of power MOSFETs. In this paper, the authors propose a MOSFET with a novel buried channel, Sandwiched Channel MOSFET (SC-MOSFET), by which the channel mobility at high gate voltage can be improved. Effects of the channel structure (thickness and doping) were experimentally investigated. Structure of SC-MOSFET Figure 1 illustrates the schematic structure of a SC-MOSFET and the band diagram of the channel region, when the gate voltage is zero. In the SC-MOSFET, the buried n-channel is sandwiched by a thin p-layer and the p-body, different from normal ACCUFET. Owing to the built-in electric field from the n-channel to the top p-layer underneath the gate oxide, more electrons can travel apart from the MOS interface, leading to higher channel mobility. It is also expected that the freedom in channel structure for realizing normally-off characteristics is larger than the normal buried-channel MOSFETs (ACCUFETs), because the channel region is depleted from both the top and bottom sides. Materials Science Forum Online: 2004-06-15 ISSN: 1662-9752, Vols. 457-460, pp 1409-1412 doi:10.4028/www.scientific.net/MSF.457-460.1409 © 2004 Trans Tech Publications Ltd, Switzerland All rights reserved. No part of contents of this paper may be reproduced or transmitted in any form or by any means without the written permission of Trans Tech Publications Ltd, www.scientific.net. (Semanticscholar.org-11/03/20,15:23:29) 2 Title of Publication (to be inserted by the publisher) Device fabrication 4H-SiC (0001) SC-MOSFETs were fabricated on a p-type epilayer with an acceptor concentration of 2.0×10 16 cm −3 . The buried channel was formed by nitrogen ion implantation at room temperature, and the channel doping concentration was varied in the range from 2.0×10 15 to 6.0×10 16 cm −3 . The thickness of the buried channel (dn) and that of the top p-layer (dp) were 0.02-0.2 μm and 0.05-0.13 μm, respectively. The source/drain regions were formed by high-dose P + implantation at 300°C. The source/drain implant dose was 7.0×10 15 cm -2 . Post-implantation anneal was carried out at 1600 °C for 20 min in Ar. For comparison, the inversion-type MOSFETs and the conventional ACCUFETs were fabricated. After RCA cleaning, oxidation in dry N2O ambient at 1300 °C was carried out. The oxide thickness was 40-50 nm. The channel length (L) and width (W) were typically 40 μm and 200 μm, respectively. Results and discussion Figure 2 shows the drain characteristics of a SC-MOSFET. The SC-MOSFET showed much higher drain current than a typical inversion-type MOSFET. The threshold voltage of the device was 0.51 V. The relationship between threshold voltage and channel structure is described later. To investigate the effect of novel channel structure, the characteristics of inversion-type MOSFET, ACCUFET and SC-MOSFET were compared. Figure 3 shows the effective channel mobility of those three differences. The threshold voltage (−6.5 V) of SC-MOSFET in this figure was almost the same as that of ACCUFET. The gate oxide of inversion-type MOSFET, ACCUFET and SC-MOSFET was prepared in dry N2O ambient at 1300 °C. The thickness of the buried channel formed by nitrogen ion implantation was 0.2 μm for both SC-MOSFET and ACCUFET. The channel doping concentration of SC-MOSFET and that of ACCUFET was 2.0×10 16 cm -3 and 8.0×10 16 cm -3 , respectively. Owing to the novel channel structure, the effective channel mobility of SC-MOSFET was higher than that of both the inversion-type MOSFET and ACCUFET. With increasing the gate voltage, the channel mobility of SC-MOSFET and ACCUFET decreased, because the band bending near the MOS interface approaches that of inversion-type MOSFET. For the SC-MOSFET, the decrease of the effective channel mobility at high gate voltage was smaller than that of ACCUFET. Fig.1 (a). Cross section of new structure 4H-SiC SC−MOSFET, (b). Band diagram of the channel region at zero-gate vias. n + Source Drain Gate SiO2

Molecular beam epitaxy of GaN on lattice-matched ZrB2 substrates using low-temperature GaN and AlN nucleation layers

Abstract: GaN epilayers have been grown by plasma-assisted molecular-beam epitaxy on ZrB2 substrates with close in-plane lattice match. Growth processes utilizing both low-temperature GaN (LT-GaN) and AlN nucleation layers were investigated. The x-ray ω-scan widths for the optimized LT-GaN nucleation process were 400 and 750 arcsec for symmetric and asymmetric reflections, respectively. When using LT-GaN nucleation layers, the chemical incompatibility of ZrB2 results in a high dislocation density despite the in-plane lattice match. The epilayer polarity was N-polar for LT-GaN nucleation layers under all conditions investigated. For AlN nucleation layers, Ga-polar epilayers were obtained under suitable conditions (Al-rich, lower nucleation temperatures) for nominal AlN thickness as low as 1 nm. From RHEED analysis it appears that a psuedomorphic Al wetting layer forms on the ZrB2 surface, and that using AlN as the nucleation layer may offer promise for reducing the epilayer defect density.