An object is to provide a semiconductor device of which a manufacturing process is not complicated and by which cost can be suppressed, by forming a thin film transistor using an oxide semiconductor film typified by zinc oxide, and a manufacturing method thereof. For the semiconductor device, a gate electrode is formed over a substrate; a gate insulating film is formed covering the gate electrode; an oxide semiconductor film is formed over the gate insulating film; and a first conductive film and a second conductive film are formed over the oxide semiconductor film. The oxide semiconductor film has at least a crystallized region in a channel region.

Semiconductor device, and manufacturing method thereof

Subtleties of advanced fabrication processes and nano-scale phenomena associated with integrated circuit miniaturization have exposed the insufficiencies of design rules. Such inadequacies have adverse impact on all parts of the integrated circuit creation flow where design rules are used. In addition, segregation of the various layout data modification steps required for deep sub-micrometer manufacturing are resulting in slack and inefficiencies. This invention describes methods to improve integrated circuit creation via the use of a unified model of fabrication processes and circuit elements that can complement or replace design rules. By capturing the interdependence among fabrication processes and circuit elements, the unified model enables efficient layout generation, resulting in better integrated circuits.

Design-manufacturing interface via a unified model

Substrate processing systems are described that have a capacitively coupled plasma (CCP) unit positioned inside a process chamber. The CCP unit may include a plasma excitation region formed between a first electrode and a second electrode. The first electrode may include a first plurality of openings to permit a first gas to enter the plasma excitation region, and the second electrode may include a second plurality of openings to permit an activated gas to exit the plasma excitation region. The system may further include a gas inlet for supplying the first gas to the first electrode of the CCP unit, and a pedestal that is operable to support a substrate. The pedestal is positioned below a gas reaction region into which the activated gas travels from the CCP unit.

Semiconductor processing system and methods using capacitively coupled plasma

An exemplary system may include a chamber configured to contain a semiconductor substrate in a processing region of the chamber. The system may include a first remote plasma unit fluidly coupled with a first access of the chamber and configured to deliver a first precursor into the chamber through the first access. The system may still further include a second remote plasma unit fluidly coupled with a second access of the chamber and configured to deliver a second precursor into the chamber through the second access. The first and second access may be fluidly coupled with a mixing region of the chamber that is separate from and fluidly coupled with the processing region of the chamber. The mixing region may be configured to allow the first and second precursors to interact with each other externally from the processing region of the chamber.

Semiconductor processing systems having multiple plasma configurations

A method of selectively etching a metal-containing film from a substrate comprising a metal-containing layer and a silicon oxide layer includes flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber, and applying energy to the fluorine-containing gas to generate a plasma in the plasma generation region. The plasma comprises fluorine radicals and fluorine ions. The method also includes filtering the plasma to provide a reactive gas having a higher concentration of fluorine radicals than fluorine ions, and flowing the reactive gas into a gas reaction region of the substrate processing chamber. The method also includes exposing the substrate to the reactive gas in the gas reaction region of the substrate processing chamber. The reactive gas etches the metal-containing layer at a higher etch rate than the reactive gas etches the silicon oxide layer.

Methods for etch of metal and metal-oxide films

A new method is provided for the creation of sub-micron gate electrode structures. A high-k dielectric is used for the gate dielectric, providing increased inversion carrier density without having to resort to aggressive scaling of the thickness of the gate dielectric while at the same time preventing excessive gate leakage current from occurring. Further, air-gap spacers are formed over a stacked gate structure. The gate structure consists of pre-doped polysilicon of polysilicon-germanium, thus maintaining superior control over channel inversion carriers. The vertical field between the gate structure and the channel region of the gate is maximized by the high-k gate dielectric, capacitive coupling between the source/drain regions of the structure and the gate electrode is minimized by the gate spacers that contain an air gap.

Gate stack for high performance sub-micron CMOS devices

Within a method for fabricating a field effect transistor (FET) device within a microelectronic fabrication there is employed for forming a gate electrode from a blanket gate electrode material layer a self aligned two step pattering method. By employing the self aligned two step patterning method for forming the gate electrode, there may be formed within the field effect transistor (FET) device a source/drain region prior to forming interposed between the source/drain region and the gate electrode an additional ion implant structure while is formed while employing as a mask the gate electrode and a permanent spacer layer formed adjacent the gate electrode. By forming within the field effect transistor (FET) device the source/drain region prior to forming the additional ion implant structure, the additional ion implant structure is formed with enhanced structural stability, and thus the field effect transistor (FET) device is fabricated with enhanced performance.

Sacrificial spacer layer method for fabricating field effect transistor (FET) device

Within a method for fabricating a field effect transistor (FET) device there is provided a series of ion implant methods which provide the field effect transistor (FET) device with both: (1) a source region asymmetrically doped with respect to a drain region; and (2) an asymmetrically doped channel region. The field effect transistor (FET) device is fabricated with enhanced performance.

Method for fabricating field effect transistor (FET) device with asymmetric channel region and asymmetric source and drain regions

Disclosed is a semiconductor radio frequency (RF) device having a shielding structure for minimizing coupling between RF passive components and conductive routing for active components. In one example, the device includes at least one shielding layer formed between the RF passive components and conductive routing. The shielding layer includes at least one opening. In another example, a second shielding layer may be used. The second shielding layer may also have an opening, and the openings in the first and second shielding layers may be offset from one another. The first and second shielding layers may be connected to each other through a guard ring, and may also be connected to a common voltage potential.

Device and method for providing shielding in radio frequency integrated circuits to reduce noise coupling

Provided is a semiconductor transistor device including a substrate having at least two regions, a semiconductive region extending to a first surface of the substrate and an insulative region extending to a second surface of the substrate. The semiconductor transistor device also includes a patterned semiconductor structure overlying both surfaces of the substrate. The patterned semiconductor structure includes a source or drain region overlying the second surface of the substrate. The semiconductor transistor device further includes a patterned gate structure overlying the patterned semiconductor structure.

Jyh-Chyurn Guo

Papers

Gate stack for high performance sub-micron CMOS devices

Sacrificial spacer layer method for fabricating field effect transistor (FET) device

Method for fabricating field effect transistor (FET) device with asymmetric channel region and asymmetric source and drain regions

Device and method for providing shielding in radio frequency integrated circuits to reduce noise coupling

Method of fabricating a non-floating body device with enhanced performance