Patent
Gate stack for high performance sub-micron CMOS devices
TLDR
In this article, a gate structure consisting of pre-doped polysilicon was constructed with a high-k gate dielectric, and air-gap spacers were formed over a stacked gate structure.Abstract:
A new method is provided for the creation of sub-micron gate electrode structures. A high-k dielectric is used for the gate dielectric, providing increased inversion carrier density without having to resort to aggressive scaling of the thickness of the gate dielectric while at the same time preventing excessive gate leakage current from occurring. Further, air-gap spacers are formed over a stacked gate structure. The gate structure consists of pre-doped polysilicon of polysilicon-germanium, thus maintaining superior control over channel inversion carriers. The vertical field between the gate structure and the channel region of the gate is maximized by the high-k gate dielectric, capacitive coupling between the source/drain regions of the structure and the gate electrode is minimized by the gate spacers that contain an air gap.read more
Citations
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Semiconductor device, and manufacturing method thereof
TL;DR: In this article, the oxide semiconductor film has at least a crystallized region in a channel region, which is defined as a region of interest (ROI) for a semiconductor device.
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Jang-Gyoo Yang,Matthew L. Miller,Xinglong Chen,Kien N. Chuc,Qiwei Liang,Shankar Venkataraman,Dmitry Lubomirsky +6 more
TL;DR: In this paper, a capacitively coupled plasma (CCP) unit is described inside a process chamber, and a pedestal is positioned below a gas reaction region into which the activated gas travels from the CCP unit.
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TL;DR: In this paper, a method of selectively etching a metal-containing film from a substrate comprising a metal containing layer and a silicon oxide layer is proposed, which involves flowing a fluorine-containing gas into a plasma generation region of a substrate processing chamber, and applying energy to the fluorinecontaining gas to generate a plasma in the plasma generation area.
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Methods for etch of sin films
TL;DR: In this paper, a method of selectively etching silicon nitride from a substrate comprising a silicon oxide layer and a silicon dioxide layer is proposed. But the method requires the substrate to be exposed to the reactive gas in the gas reaction region of the substrate processing chamber.
References
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PatentDOI
Lithographic template and method of formation and use
TL;DR: In this paper, a lithographic template is used in the fabrication of a semiconductor device for affecting a pattern in the device by positioning the template in close proximity to the semiconductor devices having a radiation sensitive material formed thereon and applying a pressure to cause the radiation-sensitive material to flow into the relief image present on the template.
Patent
Method for increasing gate capacitance by using both high and low dielectric gate material
TL;DR: In this article, a method for fabricating a MOSFET device is provided, which includes a step of fining a gate oxide including first and second gate oxide materials, and the first gate oxide material has a high dielectric constant and provides for forming a thick gate oxide over a channel region of the device.
Proceedings ArticleDOI
16 nm planar NMOSFET manufacturable within state-of-the-art CMOS process thanks to specific design and optimisation
Frederic Boeuf,Thomas Skotnicki,Stephane Monfray,C. Julien,Didier Dutartre,J. Martins,Pascale Mazoyer,R. Palla,B. Tavel,P. Ribot,E. Sondergard,A. Sanquer +11 more
TL;DR: In this article, a non-overlapped SD/gate architecture with channel doping has been used and shown to not only perform equally as well as the overlapped one, but also shows 1000/spl times/ reduced dispersion and is easily manufacturable.
Patent
MOSFET with suppressed gate-edge fringing field effect
TL;DR: In this paper, a method of fabricating an integrated circuit with less susceptibility to gate-edge fringing field effect is disclosed, which can be used for P-channel or N-channel metal oxide field semiconductor effect transistors (MOSFETs).
Proceedings ArticleDOI
A gate-side air-gap structure (GAS) to reduce the parasitic capacitance in MOSFETs
TL;DR: In this article, a gate-side air gap structure (GAS) was proposed for MOSFETs to reduce the fringe capacitance by half, and the gate delay was reduced by 4.8 psec at FO=1 and 16 psec in a 0.25 /spl mu/m CMOS.