技術解説 IEEE Computer

Recursive Diagonal Torus (RDT), a class of interconnection network is proposed for massively parallel computers with up to 2/sup 16/ nodes. By making the best use of a recursively structured diagonal mesh (torus) connection, the RDT has a smaller diameter (e.g., it is 11 for 2/sup 10/ nodes) with a smaller number of links per node (i.e., 8 links per node) than those of the hypercube. A simple routing algorithm, called vector routing, which is near-optimal and easy to implement is also proposed. Although the congestion on upper rank tori sometimes degrades the performance under the random traffic, the RDT provides much better performance than that of a 2D/3D torus in most cases and, under hot spot traffic, the RDT provides much better performance than that of a 2D/3D/4D torus. The RDT router chip which provides a message multicast for maintaining cache consistency is available. Using the 0.5 /spl mu/m BICMOS SOG technology, versatile functions, including hierarchical multicasting, combining acknowledge packets, shooting down/restart mechanism, and time-out/setup mechanisms, work at a 60 MHz clock rate.

Recursive diagonal torus: an interconnection network for massively parallel computers

Performance estimation is essential for designing and investigating new architectures including multiprocessors. Software simulation is one of the most common methods, since there is no limitation on device technology nor hardware configuration. Although lots of software simulators have been developed and used, they must be modified for each distinct target system. For designers of new architectures, it is often a cumbersome job. ISIS, an architecture independent simulation kit for multiprocessors, is developed so as to reduce such designers load. It includes various small simulators called "Units" corresponding to processors, buses, memories, caches and I/O devices. ISIS users can build simulators for their original target architectures only by connecting "Units" each other. The implementation cost is much reduced with little runtime overhead. A sample instruction-level multiprocessor simulator which has 4 processors can be executed 40000 to 70000 steps per second. This paper also reports experimental results of ISIS in various research projects.

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Environment for multiprocessor simulator development

We propose a method for dynamic security-domain scaling on SMPs that offers both highly scalable performance and high security for future high-end embedded systems. Its most important feature is its highly efficient use of processor resources, accomplished by dynamically changing the number of processors within a security-domain (i.e., dynamically yielding processors to other security-domains) in response to application load requirements. Two new technologies make this scaling possible without any virtualization software: (1) self-transition management and (2) unified virtual address mapping. Evaluations show that this domain control provides highly scalable performance and incurs almost no performance overhead in security-domains. The increase in OSs in binary code size is less than 1.5p, and the time required for individual state transitions is on the order of a single millisecond. This scaling is the first in the world to make possible the dynamic changing of the number of processors within a security-domain on an ARM SMP.

Dynamic security domain scaling on embedded symmetric multiprocessors

This paper describes the intelligent cache controller of JUMP-I, a distributed shared memory type MPP. JUMP-I adopts an off-the-shelf superscalar as the element processor to meet the requirement of peak performance, but such a processor lacks the ability to hide inter-processor communication latency, which may easily become too long on MPPs. Therefore JUMP-I provides an intelligent memory system to remedy the weak point. The cache controller is one of the main components of the memory system, and provides many cache-level supports for inter-processor communication; explicit cache control, high-bandwidth cache prefetching, and a few types of synchronization structures for fine-grained message communication.

The Intelligent Cache Controller of a Massively Parallel Processor JUMP-1

A massively parallel processor called JUMP-1 has been developed to build an efficient cache coherent-distributed shared memory (DSM) on a large system with more than 1000 processors. Here, the dedicated processor called MBP (Memory Based Processor)-light to manage the DSM of JUMP-1 is introduced, and its preliminary performance with two protocol policies-update/invalidate-is evaluated. From results of its simulation, it appears that simple operations like the tag check and the collection/generation of acknowledgment packets are mostly processed by the hardware mechanisms in MBP-light without the aids of the core processor with both policies. Also, the buffer-register architecture adopted by the core processor in MBP-light is exploited enough to process a protocol transaction for both policies.

/pdf/the-preliminary-evaluation-of-mbp-light-with-two-protocol-2yyzo9u3ch.pdf

K. Anjo

Papers

The preliminary evaluation of MBP-light with two protocol policies for a massively parallel processor-JUMP-1