技術解説 IEEE Computer

Recursive Diagonal Torus (RDT), a class of interconnection network is proposed for massively parallel computers with up to 2/sup 16/ nodes. By making the best use of a recursively structured diagonal mesh (torus) connection, the RDT has a smaller diameter (e.g., it is 11 for 2/sup 10/ nodes) with a smaller number of links per node (i.e., 8 links per node) than those of the hypercube. A simple routing algorithm, called vector routing, which is near-optimal and easy to implement is also proposed. Although the congestion on upper rank tori sometimes degrades the performance under the random traffic, the RDT provides much better performance than that of a 2D/3D torus in most cases and, under hot spot traffic, the RDT provides much better performance than that of a 2D/3D/4D torus. The RDT router chip which provides a message multicast for maintaining cache consistency is available. Using the 0.5 /spl mu/m BICMOS SOG technology, versatile functions, including hierarchical multicasting, combining acknowledge packets, shooting down/restart mechanism, and time-out/setup mechanisms, work at a 60 MHz clock rate.

Recursive diagonal torus: an interconnection network for massively parallel computers

Performance estimation is essential for designing and investigating new architectures including multiprocessors. Software simulation is one of the most common methods, since there is no limitation on device technology nor hardware configuration. Although lots of software simulators have been developed and used, they must be modified for each distinct target system. For designers of new architectures, it is often a cumbersome job. ISIS, an architecture independent simulation kit for multiprocessors, is developed so as to reduce such designers load. It includes various small simulators called "Units" corresponding to processors, buses, memories, caches and I/O devices. ISIS users can build simulators for their original target architectures only by connecting "Units" each other. The implementation cost is much reduced with little runtime overhead. A sample instruction-level multiprocessor simulator which has 4 processors can be executed 40000 to 70000 steps per second. This paper also reports experimental results of ISIS in various research projects.

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Environment for multiprocessor simulator development

This text features the development of the fundamental technologies for massively parallel processing, covering research on the applications, the language, the operating system and the hardware architecture. The text also addresses the present status of the system and future plans. The following topics are discussed in the section on applications: the MGCG Method; parallelization of FEM; modelling of group behaviours; parallel visualization; functional memory-type parallel processing; a parallel reduction algorhythm and combination algorhythm. As for the programming languages, the SIMD-based language NCX, the dataflow-based language V and the parallel object-oriented language A-NETL are discussed. In the chapter on operating systems, the subjects addressed are: design, philosophy and objectives; and COS software architecture and elements of the operating system. Finally, in relation to hardware architecture, the text covers: an overview of the JUMP-1 sytem; memory architecture; network architecture; I/O architecture and implementation issues. This processing system is expected to play a crucial role in the development of almost all advanced technologies for the 21st century, and this book aims to aid with research in the field of parallel processing.

The massively parallel processing system JUMP-1

We propose a method for dynamic security-domain scaling on SMPs that offers both highly scalable performance and high security for future high-end embedded systems. Its most important feature is its highly efficient use of processor resources, accomplished by dynamically changing the number of processors within a security-domain (i.e., dynamically yielding processors to other security-domains) in response to application load requirements. Two new technologies make this scaling possible without any virtualization software: (1) self-transition management and (2) unified virtual address mapping. Evaluations show that this domain control provides highly scalable performance and incurs almost no performance overhead in security-domains. The increase in OSs in binary code size is less than 1.5p, and the time required for individual state transitions is on the order of a single millisecond. This scaling is the first in the world to make possible the dynamic changing of the number of processors within a security-domain on an ARM SMP.

Dynamic security domain scaling on embedded symmetric multiprocessors

The shared cache structures and snoop cache structures for single-chip multiprocessors are evaluated and compared using an instruction level simulator. Simulation results show that 1-port large shared cache achieves the best performance if there is no delay penalty for arbitration and accessing the bus. However, if 1-clock delay is assumed for accessing the shared cache, a snoop cache with internal wide bus and invalidate style NewKeio protocol overcomes shared caches.

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Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors

A massively parallel processor called JUMP-1 has been developed to build an efficient cache coherent-distributed shared memory (DSM) on a large system with more than 1000 processors. Here, the dedicated processor called MBP (Memory Based Processor)-light to manage the DSM of JUMP-1 is introduced, and its preliminary performance with two protocol policies-update/invalidate-is evaluated. From results of its simulation, it appears that simple operations like the tag check and the collection/generation of acknowledgment packets are mostly processed by the hardware mechanisms in MBP-light without the aids of the core processor with both policies. Also, the buffer-register architecture adopted by the core processor in MBP-light is exploited enough to process a protocol transaction for both policies.

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The preliminary evaluation of MBP-light with two protocol policies for a massively parallel processor-JUMP-1

In this paper, architecture independent software simulation kit for multiprocessors called ISIS is proposed and designed. It includes various small simulators of a hardware device. All functions are implemented in C++ language, and the extension of them is also easy. Execution speed of a sample simulator was measured. Execution time of the simulator with four R3000 processors is 22,000 times of the real hardware (target system is assumed to work with 500MHz system clock). It is reasonable speed to evaluate a real multiprocessor.

ISIS: Multiprocessor Simulator Library.

To develop multiprocessor systems for continuing the precipitous increase in performance seen in recent years, it is important to include performance prediction at a preimplementation stage. Since software simulation, which is one such performance prediction technique, has a high degree of flexibility, it is used in diverse situations. To simulate a multiprocessor system, a simulator is implemented for a specific architecture. However, this method has accompanying implementation costs for building a simulator for each different target architecture. In this paper, the authors propose the multiprocessor simulator library ISIS as a multiprocessor simulator construction support system. ISIS is a collection of multiprocessor system internal function block simulators. Multiprocessor simulators having any kind of architecture can be constructed by combining function block simulators. Compared with conventional techniques, implementation costs can be reduced without directly impairing simulator runtime costs. Several multiprocessor simulators were implemented by using ISIS, and their execution speeds and implementation costs were evaluated. Sufficient runtime speeds were obtained for practical uses at extremely low implementation costs. ISIS has actually been used in research for on-chip multiprocessor cache systems, and various kinds of knowledge have been obtained from the evaluation results of that research. © 2003 Wiley Periodicals, Inc. Electron Comm Jpn Pt 3, 86(10): 74–84, 2003; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/ecjc.10122

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Masaki Wakabayashi

Papers

Environment for multiprocessor simulator development

Shared vs. Snoop: Evaluation of Cache Structure for Single-Chip Multiprocessors

The preliminary evaluation of MBP-light with two protocol policies for a massively parallel processor-JUMP-1

ISIS: Multiprocessor Simulator Library.

Environment for multiprocessor simulator development