An experimental technique is described for observing the effects of switching transients in digital MOS circuits that perturb analog circuits integrated on the same die by means of coupling through the substrate Various approaches to reducing substrate crosstalk (the use of physical separation of analog and digital circuits, guard rings, and a low-inductance substrate bias) are evaluated experimentally for a CMOS technology with a substrate comprising an epitaxial layer grown on a heavily doped bulk wafer Observations indicate that reducing the inductance in the substrate bias is the most effective Device simulations are used to show how crosstalk propagates via the heavily doped bulk and to predict the nature of substrate crosstalk in CMOS technologies integrated in uniform, lightly doped bulk substrates, showing that in such cases the substrate noise is highly dependent on layout geometry A method of including substrate effects in SPICE simulations for circuits fabricated on epitaxial, heavily doped substrates is developed >

Experimental Results and Modeling Techniques for Substrate Noise in Mixed-Signal Integrated Circuits

A passive touch system includes a passive touch surface and at least two cameras associated with the touch surface. The at least two cameras acquire images of the touch surface from different locations and have overlapping fields of view. A processor receives and processes images acquired by the at least two cameras to detect the existence of a pointer therein and to determine the location of the pointer relative to the touch surface. Actual pointer contact with the touch surface and pointer hover above the touch surface can be determined.

Passive touch system and method of detecting user input

A 352/spl times/288 pixel CMOS image sensor chip with per-pixel single-slope ADC and dynamic memory in a standard digital 0.18-/spl mu/m CMOS process is described. The chip performs "snapshot" image acquisition, parallel 8-bit A/D conversion, and digital readout at continuous rate of 10000 frames/s or 1 Gpixels/s with power consumption of 50 mW. Each pixel consists of a photogate circuit, a three-stage comparator, and an 8-bit 3T dynamic memory comprising a total of 37 transistors in 9.4/spl times/9.4 /spl mu/m with a fill factor of 15%. The photogate quantum efficiency is 13.6%, and the sensor conversion gain is 13.1 /spl mu/V/e/sup -/. At 1000 frames/s, measured integral nonlinearity is 0.22% over a 1-V range, rms temporal noise with digital CDS is 0.15%, and rms FPN with digital CDS is 0.027%. When operated at low frame rates, on-chip power management circuits permit complete powerdown between each frame conversion and readout. The digitized pixel data is read out over a 64-bit (8-pixel) wide bus operating at 167 MHz, i.e., over 1.33 GB/s. The chip is suitable for general high-speed imaging applications as well as for the implementation of several still and standard video rate applications that benefit from high-speed capture, such as dynamic range enhancement, motion estimation and compensation, and image stabilization.

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A 10000 frames/s CMOS digital pixel sensor

This paper examines the apparent limits, possible extensions, and applications of CMOS technology in the nanometer regime. Starting from device scaling theory and current industry projections, we analyze the achievable performance and possible limits of CMOS technology from the point of view of device physics, device technology, and power consumption. Various possible extensions to the basic logic and memory devices are reviewed, with emphasis on novel devices that are structurally distinct front conventional bulk CMOS logic and memory devices. Possible applications of nanoscale CMOS are examined, with a view to better defining the likely capabilities of future microelectronic systems. This analysis covers both data processing applications and nondata processing applications such as RF and imaging. Finally, we speculate on the future of CMOS for the coming 15-20 years.

Nanoscale CMOS

In this paper, we consider a fractionally spaced equalizer (FSE) for electronic compensation of chromatic dispersion (CD) and polarization-mode dispersion (PMD) in a dually polarized (polarization-multiplexed) coherent optical communications system. Our results show that the FSE can compensate any arbitrary amount of CD and first-order PMD distortion, provided that the oversampling rate is at least 3/2 and that a sufficient number of equalizer taps are used. In contrast, the amount of CD and PMD that can be corrected by a symbol-rate equalizer only approaches an asymptotic limit, and increasing the number of taps has no effect on performance due to aliasing that causes signal cancellation and noise enhancement.

/pdf/digital-equalization-of-chromatic-dispersion-and-416m9um0kj.pdf

Digital Equalization of Chromatic Dispersion and Polarization Mode Dispersion

This chip provides programmable fractional spacings and slicers making it suitable for 51Mb/s and 155Mb/s ATM over CAT3, as well as for the emerging 100Mb/s base-T2 fast Ethernet standard. The primary design goal is to minimize the power consumption so that the equalizer may be integrated into low-cost single-chip transceivers. Two 64-tap adaptive FIR filters are configured in parallel as in-phase and quadrature filters. Each has a span of l6T, where T is the symbol period, and is programmable to operate with T/2, T/3 or T/4 fractional spacing. On-chip programmable slicers enable slicing of up to 8x8 constellations. They use a reduced constellation for blind training and switch to the full constellation to obtain final convergence. The filters feature a zero latency cascadable systolic FIR structure that has the low power advantages of the direct form due to the reduced number of flip-flops in the output path, as well as the reduced critical path advantages of the transposed form. A programmable delay synchronizes the input data with the coefficients and the error for correct least mean squares (LMS) coefficient adaption with different fractional spacings.

A low power 128-tap digital adaptive equalizer for broadband modems

A digital color camera has been monolithically realized in a standard 0.8-/spl mu/m CMOS technology. The chip integrates a 353/spl times/292 photogate sensor array with a unity-gain column circuit, a hierarchical column multiplexer, a switched-capacitor programmable-gain amplifier, and an 8-b flash analog/digital converter together with digital circuits performing color interpolation, color correction, computation of image statistics, and control functions. The 105-mm/sup 2/ chip produces 24-b RGB video at 30 frames/s. The sensor array achieves a conversion gain of 40 /spl mu/V/electron and a monochrome sensitivity of 7 V/lux/spl middot/s. For a 33-ms exposure time, the camera chip achieves a dynamic range of 65 dB and peak-to-peak fixed pattern noise that is 0.3% of saturation. Digital switching noise coupling into the analog circuits is shown to be data independent and therefore has no effect on image quality. Total power dissipation is less than 200 mW from a 3.3 V supply.

A 200 mW 3.3 V CMOS color camera IC producing 352/spl times/288 24 b video at 30 frames/s

1000BASE-T Gigabit Ethernet employs eight-state 4-dimensional trellis-coded modulation to achieve robust 1-Gb/s transmission over four pairs of Category-5 copper cabling. This paper compares several postcursor equalization and trellis decoding algorithms with respect to performance, hardware complexity, and critical path. It is shown that parallel decision-feedback decoders (PDFD) offer the best tradeoff. The example of a 14-tap PDFD, however, shows that it is challenging to meet the required throughput of 1 Gb/s using current standard-cell CMOS technology. A modified approach is proposed which uses decision-feedback prefilters followed by a one-tap PDFD. This considerably reduces hardware complexity and improves the throughput while still meeting the bit-error-rate requirement. The critical path is further reduced by employing a look-ahead technique. The proposed joint equalizer and trellis decoder architecture has been implemented in 3.3-V 0.25-/spl mu/m standard-cell CMOS process. It achieves a throughput of 1 Gb/s with a 125 MHz clock. Compared to a 14-tap PDFD, the design improves both gate count and throughput by a factor of two, while suffering only from a 1.3-dB performance degradation.

A 1-Gb/s joint equalizer and trellis decoder for 1000BASE-T Gigabit Ethernet

We present the architecture of a programmable FIR filter for use in DSP and communication applications. A filter with this architecture is capable of running a wide variety of single-rate and multirate filtering algorithms with low latency. Flexibility is achieved by distributed register files that store input data and filter coefficients. The functionality of the filter is programmed by a set of pipelined control signals that are independent of the filter length. We demonstrate how to generate these control signals for a variety of configurations. In addition to its flexibility, the architecture is scalable, modular, and has no broadcast signals, making it ideally suited for VLSI implementations.

K. Azadet

Papers

A low power 128-tap digital adaptive equalizer for broadband modems

A 200 mW 3.3 V CMOS color camera IC producing 352/spl times/288 24 b video at 30 frames/s

A 1-Gb/s joint equalizer and trellis decoder for 1000BASE-T Gigabit Ethernet

Reconfigurable hardware for efficient implementation of programmable FIR filters