This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems. The chapters on low-noise amplifiers, oscillators and phase noise have been significantly expanded as well. The chapter on architectures now contains several examples of complete chip designs that bring together all the various theoretical and practical elements involved in producing a prototype chip. First Edition Hb (1998): 0-521-63061-4 First Edition Pb (1998); 0-521-63922-0

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

This paper presents a 300-GHz transceiver based on 80-nm InP-HEMT technology. To improve the signal-to-noise-and-distortion-ratio (SNDR) characteristics, a high-isolation fundamental mixer is used in which the matching networks are designed for good RF/IF isolation to simultaneously achieve high conversion gain and feasible module packaging. The measured conversion gain of the fabricated mixer module is $-\mathbf{15}\pm \mathbf{2\ dB}$ , where the LO frequency, IF, and RF are 270, 2–32, and 272–302 GHz. The 300-GHz transceiver consists of the high-isolation mixer, 300-GHz amplifiers, and commercially available frequency multipliers as the LO source. It achieves 100-Gb/s wireless data transmission using 16QAM over a distance of 2.22 m with a 50-dBi antenna. To the best of the authors' knowledge, this is the highest wireless data rate ever achieved using only electronic devices.

300-GHz. 100-Gb/s InP-HEMT Wireless Transceiver Using a 300-GHz Fundamental Mixer

We developed a 300-GHz-band 120-Gb/s wireless transceiver front-ends (TRX) using our in-house InP-based high-electron-mobility-transistor (InP-HEMT) technology for beyond-5G. The TRX is composed of the RF power amplifiers (PAs), mixers, and local oscillation (LO) PAs which are all packaged in individual waveguide (WG) modules by using a ridge coupler for low-loss WG-to-IC transition. RF PAs are designed using the low-impedance inter-stage-matching technique to reduce the inter-stage matching loss of the amplifier stages, and the back-side DC line (BDCL) technique is used to simplify the layout and to improve the gain of the PAs. The fabricated RF PAs show a high output 1-dB compression point of more than 6 dBm from 278 to 302 GHz. The mixers are used for both up- and down-conversion in the transmitter and receiver. These mixers are designed to have high conversion gain (CG) over the wideband even after packaging by enhancing the isolation between the RF and IF ports. The measured CG of mixer module is −15 dB, and the 3-dB IF-bandwidth is 32 GHz. The LO PAs are also designed using the BDCL technique so that they can supply the required LO power to the mixers. The TRX with these InP building blocks enables the data transmission of a 120 Gb/s 16QAM signal over a link distance of 9.8 m.

300-GHz-Band 120-Gb/s Wireless Front-End Based on InP-HEMT PAs and Mixers

We present an analytical model, design, and measurement results on fundamental, harmonic, and subharmonic down conversion mixing approaches in 65-nm CMOS around and above the transistor cutoff frequency $f_{\max}$ , targeting submillimeter-wave operation. Analytical expressions for the mixing approaches are derived and compared with the simulation and measurement results. To investigate how to improve the performance of a passive mixer around and beyond $f_{\max}$ , the relation between local oscillator (LO) harmonics (including both the harmonic amplitude and phase), mixer gate bias, and conversion gain is studied. To demonstrate mixing approaches, we present integrated 160- and 280-GHz down-converters with integrated LO manufactured in 65-nm CMOS process with $f_{\max}=\hbox{ 210 GHz}$ . The LO in both down-converters is based on exploiting higher harmonics of a differential Colpitts topology voltage-controlled oscillator (VCO). Passive conversion losses of 22 and 25.5 dB are obtained over the 150–180-GHz and the 230–290-GHz frequency range, respectively. Two additional versions of the down converter at 170 and 280 GHz, respectively, without integrated VCO are also presented to examine the mixer performance in the 110–325-GHz range.

130-320-GHz CMOS Harmonic Down-Converters Around and Above the Cutoff Frequency

This article presents a packaged SiGe BiCMOS reflectometer for 0.01–26-GHz two-port vector network analyzers (VNAs). The reflectometer chip is composed of a resistive bridge coupler and two wideband heterodyne receivers for coherent magnitude and phase detection. In addition, a high-linearity receiver channel is designed to accommodate ~20 dBm of RF input power to the reflectometer. External sources are used to provide stimulus over the entire bandwidth, and a high-linearity shunt 50- $\Omega $ switch is placed at the input of each reflectometer chip to provide a matched condition for better measurement accuracy. The measured dynamic range (DR) of the heterodyne receiver is 129±3 dB at 0.01–26 GHz at an IF resolution bandwidth (RBW) of 10 Hz. The reflectometer chip is packaged on a low-cost printed circuit board (PCB) and connectorized for repeatable measurements. Several passive and active device-under-test (DUTs), such as filters and amplifiers, are measured in single- and dual-port complex $S$ -parameter setup at 0.01–26 GHz. The single-chip reflectometer results in excellent agreement with commercially available test equipment and with minimal magnitude and phase difference. Several definitions (mean deviation and error vector) are used to quantify the measurement accuracy. A measured $S_{21}$ of −80 dB is obtained using high-rejection filters. An in-depth DR analysis of possible limiting factors in the measurement setup is also presented. This article shows that silicon-based highly integrated reflectometers can be used in low-cost VNAs with excellent DR and accuracy.

A Packaged 0.01–26-GHz Single-Chip SiGe Reflectometer for Two-Port Vector Network Analyzers

In this paper, fundamental performance limits and scaling of a double-balanced passive mixer are examined. Analysis of the passive double-balanced mixer will show how its performance metrics are directly affected by the down-scaling of the transistor gate length, LG. We analyze the performance in terms of conversion gain (GC), 1-dB compression point (P1-dB) which we derive, and SSB Noise Figure (NF). We will show that as CMOS process technology evolves, the double-balanced passive mixer architecture will become more favorable and yield improved performance. This is verified through simulation and modeling results for mixers designed in CMOS 350 nm to 32 nm technology. We introduce a mixerpsilas figure-of-merit (FOMMIXER) to compare performance with technology scaling. Circuit designers and system architects can use this paper to find a suitable process technology that will meet their specifications.

Fundamental performance limits and scaling of a CMOS passive double-balanced mixer

In this paper, modeling, simulation, and implementation of double-balanced passive mixer are shown and examined. We analyze the performance of the mixer in terms of conversion gain (GC), 1-dB compression point, and noise figure (NF). We will show the accuracy of our model and analyses when compared with simulation and measured results for a 130 nm technology based mixer design. We introduce a mixerpsilas figure-of-merit (FOMMIXER) and briefly show that as CMOS process technology evolves, the double-balanced passive mixer architecture will become more favorable and yield improved performance.

K. Komoni

Papers

Fundamental performance limits and scaling of a CMOS passive double-balanced mixer

Modeling, simulation and implementation of a passive mixer in 130nm CMOS technology and scaling issues for future technologies