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Proceedings ArticleDOI

Fundamental performance limits and scaling of a CMOS passive double-balanced mixer

TLDR
It is shown that as CMOS process technology evolves, the double-balanced passive mixer architecture will become more favorable and yield improved performance.
Abstract
In this paper, fundamental performance limits and scaling of a double-balanced passive mixer are examined. Analysis of the passive double-balanced mixer will show how its performance metrics are directly affected by the down-scaling of the transistor gate length, LG. We analyze the performance in terms of conversion gain (GC), 1-dB compression point (P1-dB) which we derive, and SSB Noise Figure (NF). We will show that as CMOS process technology evolves, the double-balanced passive mixer architecture will become more favorable and yield improved performance. This is verified through simulation and modeling results for mixers designed in CMOS 350 nm to 32 nm technology. We introduce a mixerpsilas figure-of-merit (FOMMIXER) to compare performance with technology scaling. Circuit designers and system architects can use this paper to find a suitable process technology that will meet their specifications.

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Book ChapterDOI

The Design of CMOS Radio-Frequency Integrated Circuits: RF CIRCUITS THROUGH THE AGES

Thomas H. Lee
TL;DR: In this paper, an expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Proceedings ArticleDOI

300-GHz. 100-Gb/s InP-HEMT Wireless Transceiver Using a 300-GHz Fundamental Mixer

TL;DR: A high-isolation fundamental mixer is used in which the matching networks are designed for good RF/IF isolation to simultaneously achieve high conversion gain and feasible module packaging to improve the signal-to-noise-and-distortion-ratio (SNDR) characteristics.
Journal ArticleDOI

300-GHz-Band 120-Gb/s Wireless Front-End Based on InP-HEMT PAs and Mixers

TL;DR: A 300-GHz-band 120-Gb/s wireless transceiver front-ends (TRX) using the in-house InP-based high-electron-mobility-transistor (InP-HEMT) technology for beyond-5G is developed.
Journal ArticleDOI

A Packaged 0.01–26-GHz Single-Chip SiGe Reflectometer for Two-Port Vector Network Analyzers

TL;DR: In this article, a SiGe BiCMOS reflectometer for 0.01-26 GHz two-port vector network analyzers (VNAs) is presented, which is composed of a resistive bridge coupler and two wideband heterodyne receivers for coherent magnitude and phase detection.
Journal ArticleDOI

A 60 GHz Low Power Self-mixing Receiver in 65-nm CMOS for a Radio-Triggered Battery-Less Monolithic Wireless Sensor

TL;DR: A system of radio-triggered batteryless monolithic wireless sensor based on mm-wave wireless power transfer technique is introduced in this work, and the sensitivity of the receiver is improved by applying the IJLO into the self-mixing architecture.
References
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Journal Article

The design of CMOS radio-frequency integrated circuits, 2nd edition

TL;DR: This expanded and thoroughly revised edition of Thomas H. Lee's acclaimed guide to the design of gigahertz RF integrated circuits features a completely new chapter on the principles of wireless systems.
Book

The Design of CMOS Radio-Frequency Integrated Circuits

TL;DR: In this article, the authors present an expanded and thoroughly revised edition of Tom Lee's acclaimed guide to the design of gigahertz RF integrated circuits, which is packed with physical insights and design tips, and includes a historical overview of the field in context.
Journal ArticleDOI

A precise four-quadrant multiplier with subnanosecond response

TL;DR: Among the most signficant presentations in the 50-year history of the ISSCC, Barrie Gilbert's classic paper has become the fifth most frequently cited JSSC article and the first to be cited over 100 times.
Journal ArticleDOI

RF-CMOS performance trends

TL;DR: In this paper, the impact of scaling on the analog performance of MOS devices at RF frequencies was studied and a scaling methodology for RF-CMOS based on limited linearity degradation was proposed.