In this paper, a set up noise parameter expression and the third order intermodulation product expression (IM3) for a power-constrained simultaneous noise and input matching low noise amplifier design optimization technique are introduced. Based on these expressions, the methodology to design LNA to archive the power-constrained simultaneous noise and input matching as well as satisfy the linearization condition is explained. In additional, the power gain is enhanced by using a very simple positive feedback. The proposed LNA for 5 GHz WLAN applications is fabricated based on 0.18 /spl mu/m CMOS technology. Measured results show 20 dB power gain, 1.5 dB NF and -5 dBm IIP3. The proposed LNA dissipates DC current of 3 mA at supply voltage of 2.5 V.

CMOS low noise amplifier design optimization technique

A differential voltage-controlled oscillator has been designed to operate in the 10 GHz band using a 0.25 /spl mu/m CMOS process and low Q integrated inductors. The low gain and low Q problems of the components are overcome by the deployment of the cascode configuration with negative conductance generation to enhance the loop gain and Q value. PMOS varactors are used for varying the oscillating frequency from 9.7 to 11.4 GHz. The phase noise at 400 kHz offset is from -101 dB/Hz at the low frequency end to -87 dB/Hz at the high frequency end.

Fully integrated 10 GHz CMOS VCO

An experimental filter was designed to operate at 3.6 GHz using mainstream 0.18 µm CMOS. In the design, the Q-enhancement technique was used to overcome the low-Q characteristics of the CMOS on-chip inductors. A sixth-order bandpass filter with a wide passband and a high image rejection was built by cascading three stages of second-order Q-enhanced filters. A combination of three biquads with oset in center frequency provides wider tuning frequency and bandwidth. This high-performance filter provides a 340 MHz tunable center frequency around 3.6 GHz, an image rejection of 50 dB and a tunable Q from 25 to 50 for a bandwidth adjustment from 95 MHz to 35 MHz. The filter achieves an 18 dB voltage gain while consuming 130 mW of power at 1.8 V DC supply. The chip occupies an area of 900 × 900 µm2 including all the required bonding pads. The design provides a simple architecture to simplify tuning scheme for both frequency and bandwidth for practical use. The tunable ability of the design could be exploited in further study to be used as a channel-select filter in the gigahertz range.

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A Q-enhanced 3.6 GHz, tunable, sixth-order bandpass filter using 0.18 µm CMOS

High Performance Continuous-time Filters for Information Transfer Systems. (August 2003) Ahmed Nader Mohieldin, B.Sc., Cairo University, Egypt; M.Sc., Cairo University, Egypt; Chairs of Advisory Committee: Dr. Edgar Sánchez-Sinencio Vast attention has been paid to active continuous-time filters over the years. The changes in technology have required new approaches. Thus as cheap, readily available integrated circuit OpAmps replaced their discrete circuit versions, it became feasible to consider active-RC filter circuits using large numbers of OpAmps, and new improved architectures emerged. Similarly the development of integrated operational Transconductnace Amplifier (OTA) led to new filter configurations and allowed practical solutions to problems using currents as the variables of interest, rather than voltages. That is trasconductance-mode. This gives rise to OTA-C filters, using only active devices and capacitors, making it more suitable for integration. The demands on filter circuits have become ever more stringent as the world of electronics and communications has advanced. In addition, the continuing increase in the operating frequencies of modern circuits and systems increases the need for active filters that can perform at these higher frequencies; an area where the LC active filter emerges. What mainly limit the performance of an analog circuit are the non-idealities of the used building blocks and the circuit architecture. The research is concentrating on the design issues of high frequency continuous-time integrated filters. Several novel circuit building blocks are introduced. A novel pseudo-differential fully balanced fully symmetric CMOS OTA architecture with inherent common-mode detection is proposed. Through judicious arrangement, the common-mode feedback circuit can be economically implemented. On the level of system architectures, a novel filter low-voltage 4 order RF bandpass filter structure based on emulation of two magnetically coupled resonators is presented. A unique feature of the proposed architecture is using electric coupling to emulate the effect of the coupled-inductors, thus providing bandwidth tuning with small passband ripple. Each resonator is built using on-chip spiral inductors and accumulation-mode PMOS capacitors to provide center frequency tuning. As part of a direct conversion dual-mode 802.11b/Bluetooth receiver, a BiCMOS 5 order low-pass channel selection filter is designed. The filter operated from single 2.5V supply and achieves 76dB of out-of-band SFDR. A digital automatic tuning system is also implemented to account for process and temperature variations. As part of a Bluetooth transmitter, a low-power quadrature direct digital frequency synthesizer (DDFS) is presented. Piecewise linear approximation is used to avoid using ROM look-up table to store the sine values in a conventional DDFS. Significant saving in power consumption, due to the elimination of the ROM, renders the design more suitable for portable wireless communication applications.

High performance continuous-time filters for information transfer systems

This paper presents a sub-mA, low-noise, high-gain CMOS low noise amplifier (LNA) for 2.4-GHz band applications based on 0.18 /spl mu/m CMOS technology. Low-noise under power-constrained can be achieved by using an inductive cascode degeneration amplifier with an extra gate-source capacitor. Gain enhancement can be obtained by using capacitive feedback at the cascode transistor. Measurements show 16 dB gain, 1.8 dB NF, -10 dBm IIP3 while dissipating only 0.5 mA from 1.5 V supply.

A sub-mA, high-gain CMOS low-noise amplifier for 2.4 GHz applications

To have a fully integrated communication system in CMOS, a CMOS bandpass amplifier which combines the functions of low noise amplifier (LNA) and bandpass filter (BPF) is necessary. In a conventional bandpass amplifier, a Q-enhancement circuit is required to compensate for the resistive loss in the integrated inductor. The Q-enhancement circuit, however, being active, increases the power consumption (P/sub d/) and noise figure (NF) of the system. In the paper, a new bandpass amplifier has been proposed which can achieve the required Q without an additional Q-enhancement circuit. Comparison with other recent designs shows that the proposed amplifier has the lowest P/sub d/ and the best noise performance. Based on the CSM 0.25 /spl mu/m CMOS process, the bandpass amplifier has a gain of 25.3 dB, a Q of 30, an NF of 3.56 dB and a P/sub d/ of 35.7 mW at 1.8 GHz.

K.-L. Chan

Papers

1.5 V 1.8 GHz bandpass amplifier