K. Lilja

TL;DR: In this paper, alpha, neutron, and heavy ion single event measurements were performed on both high-performance and hardened flip-flop designs in a 28-nm bulk CMOS technology.

TL;DR: In this paper, heavy ion experimental results from flip-flops in 180-nm to 28-nm bulk technologies are used to quantify single-event upset trends, and the results show that as technologies scale, D flipflop single event upset cross sections decrease while redundant storage node flipflops cross sections may stay the same or increase depending on the layout spacing of storage nodes.

TL;DR: In this article, D-flip-flop designs hardened with stacked transistors for a 32-nm SOI CMOS technology show greater than three orders of magnitude decrease in soft error cross-section, up to a heavy-ion tested tilt angle of 55°, and greater than one order of magnitude increase in cross-sectional area for a heavy ion tested tilt-angle of 75° with less than 50% area penalty compared to unhardened D-FLIP-FLop designs.

TL;DR: In this article, a variety of flip-flop (FF) designs fabricated in a commercial 28-nm Fully-Depleted Silicon on Insulator (FDSOI) technology are evaluated for their single-event upset performance with ions and pulsed laser experiments.

TL;DR: In this article, stacked-transistor structures are introduced in the stacked Quatro design to protect the sensitive devices of the original structure, and irradiation experimental results substantiate that the stacked quatro design has significantly better SEU tolerance (e.g., higher heavy ion upset Linear Energy Transfer threshold and smaller cross-section data) than the reference designs.